SNAS605AR – MARCH 2013 – REVISED DECEMBER 2015
9.3.3.2 Dynamic Digital Delay
Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the
clock signal. This is accomplished by substituting the regular clock divider with an alternate divide value for one
cycle. This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT
field for all outputs with DDLYdX_EN = 1.
•
By programming a larger alternate divider (delay) value, the phase of the adjusted outputs will be delayed
with respect to the other clocks.
•
By programming a smaller alternate divider (delay) value, the phase of the adjusted output will advanced with
respect to the other clocks.
shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting
for delay by one VCO cycle. The clock will output high during the DCLKoutX_DDLY_CNTH time to permit a
continuous output clock. The clock output will be low during the DCLKoutX_DDLY_CNTL time.
Table 3. Recommended DCLKoutX_DDLY_CNTH/_CNTL Values for Delay by One VCO Cycle
CLOCK DIVIDER
_CNTH
_CNTL
CLOCK DIVIDER
_CNTH
_CNTL
2
2
3
17
9
9
3
3
4
18
9
10
4
2
3
19
10
10
5
3
3
20
10
11
6
3
4
21
11
11
7
4
4
22
11
12
8
4
5
23
12
12
9
5
5
24
12
13
10
5
6
25
13
13
11
6
6
26
13
14
12
6
7
27
14
14
13
7
7
28
14
15
14
7
8
29
15
15
15
8
8
30
15
16
(1)
16
8
9
31
16
(1)
16
(1)
(1)
To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field.
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