Texas Instruments ISO7220 Series, Руководство пользователя

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1.5 The ISO7221x EVM Configuration
INA
OUTB
R8
R4
R6
INB
OUTA
R2
INA
OUTB
R7
R1
OUTA
INB
Introduction
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The ISO7221x EVM configuration has SMA connectors (J4 and J1) set up as the input to the INA (pin 7)
and INB (pin 3) of the ISO7221x in
Figure 1 and Figure 3 . R2 and R6 are 0-
Ω
input series resistors shown
in Figure 6 , and are located next to the J1 and J4 input connectors.
Figure 6. The ISO7221x EVM Top View
The output channel configuration of the ISO7221x EVM has the OUTA (pin 2) and OUTB (pin 6) of
Figure 1 and Figure 3 connected to SMA connector (J3 and J2) through 0-
Ω
series resistor, R8 and R4 .
R1 and R7 are 50-
Ω
resistors from each input to ground on the bottom of the board shown in Figure 7 .
Figure 7. The ISO7221x EVM Bottom View
The pads for R3, R5, C1, C12, C13 and C14 are available on the bottom of the EVM for varied loading
conditions if desired by a user.
Dual-Channel Digital Isolator EVM 6 SLLU098A – June 2007 – Revised July 2009
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