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1.1

Overview

1.2

Functional Configuration of the Dual-Channel Digital Isolator

ISO7221x

1

2

3

4

5

6

7

8

GND2

Vcc2

Vcc1

GND1

OUTB

INA

OUTA

INB

IS

O

L

A

T

IO

N

ISO7220x

1

2

3

4

5

6

7

8

GND2

Vcc2

Vcc1

GND1

OUTB

INA

OUTA

INB

IS

O

L

A

T

IO

N

Introduction

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The ISO7220x and ISO721x dual digital isolators have a logic input and output buffer separated by a
silicon oxide (SiO

2

) insulation barrier. Used in conjunction with isolated power supplies, these devices

block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from
entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, and then differentiated by the
capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic
transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update
pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not
received for more than 4

µ

s, the input is assumed to be unpowered or not functional, and the failsafe

circuit drives the output to a logic-high state.

CAUTION

Note that although these devices provide galvanic isolation of up to 4000 V, this
EVM cannot be used for isolation voltage testing. It is designed for the
examination of device operating parameters only and will be damaged if high
voltage (> 5.5 V) is applied anywhere in the circuit.

The pin-outs of the dual-channel digital isolators are displayed in

Figure 1

The EVM comes with an

ISO7220M installed; however, the user may reconfigure the EVM for use with any of the footprints.

Figure 1. The ISO7220x and ISO7221x Pinouts

The ISO7220A, ISO7220B, ISO7220C, ISO7221A, ISO7221B and ISO7221C have TTL input thresholds
and an input noise filter that prevents transient pulses of up to 2 ns in duration from being passed to the
output of the device.

The ISO7220M and ISO7221M have a CMOS Vcc/2 input threshold, but do not have the noise filter and
the additional propagation delay.

Dual-Channel Digital Isolator EVM

2

SLLU098A – June 2007 – Revised July 2009

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Содержание ISO7220 Series

Страница 1: ...m View 6 8 Basic EVM Operation 7 9 Typical Input and Output Waveforms 7 List of Tables 1 ISO7220x EVM Connections 3 2 ISO7221x EVM Connections 4 This user s guide details the evaluation module EVM operation of the factory installed ISO7220M dual channel digital isolator However the EVM board may be reconfigured by a user for use with any of the ISO7220x or ISO7221x dual channel isolators The EVM m...

Страница 2: ...he proper dc level of the output If this dc refresh pulse is not received for more than 4 µs the input is assumed to be unpowered or not functional and the failsafe circuit drives the output to a logic high state CAUTION Note that although these devices provide galvanic isolation of up to 4000 V this EVM cannot be used for isolation voltage testing It is designed for the examination of device oper...

Страница 3: ...l isolators Figure 2 The ISO7220x Same Channel Direction Schematic Table 1 ISO7220x EVM Connections Connection Label Description J1 SMA connector to the INB input pin 3 J2 SMA connector to the OUTB output pin 6 J3 SMA connector to the INA input pin 2 J4 SMA connector to the OUTA output pin 7 P1 VCC1 Input power supply banana jack P2 VCC2 Output power supply banana jack P3 GND1 Input power ground c...

Страница 4: ...bel Description J1 SMA connector to the INB input pin 3 J2 SMA connector to the OUTB output pin 6 J3 SMA connector to the OUTA output pin 2 J4 SMA connector to the INA input pin 7 P1 VCC1 Input power supply banana jack P2 VCC2 Output power supply banana jack P3 GND1 Input power ground connection banana jack P4 GND2 Output power ground connection banana jack JMP1 3 pin jumper VCC1 input GND1 JMP2 3...

Страница 5: ...are 50 Ω resistors from each input to ground and are located on the bottom of the board as shown in Figure 5 Figure 4 ISO7220x EVM Top View The output channel configuration of the ISO7220x EVM has the OUTA pin 7 and OUTB pin 6 of Figure 1 and Figure 2 connected to SMA connector J2 and J4 through 0 Ω series resistor R4 and R6 Figure 5 ISO7220x EVM Bottom View The pads for R3 R7 C1 C12 C13 and C14 a...

Страница 6: ...e 6 The ISO7221x EVM Top View The output channel configuration of the ISO7221x EVM has the OUTA pin 2 and OUTB pin 6 of Figure 1 and Figure 3 connected to SMA connector J3 and J2 through 0 Ω series resistor R8 and R4 R1 and R7 are 50 Ω resistors from each input to ground on the bottom of the board shown in Figure 7 Figure 7 The ISO7221x EVM Bottom View The pads for R3 R5 C1 C12 C13 and C14 are ava...

Страница 7: ... If both sides are to be evaluated at the same supply voltage only one power supply is required and can be used to power both sides of the EVM CAUTION Note that this EVM is for operating parameter performance evaluation only and not designed for isolation voltage testing Any voltage applied above the 5 5 V maximum recommended operating voltage of the digital isolators will damage the EVM Figure 8 ...

Страница 8: ...t temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used FCC Warning This evaluation...

Страница 9: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

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