4.12 NAND Flash Control Register (NANDFCR)
4-12
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 4—Registers
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4.12 NAND Flash Control Register (NANDFCR)
The NANDFCR register is shown in
and described in
.
Figure 4-8
NAND Flash Control Register (NANDFCR)
31
14
13
12
11
Reserved
ADDR_CALC_START
4BIT_ECC_START
CS5_ECC_START
R - 0x0
RW -
RW -
RW -
10
9
8
7
6
CS4_ECC_START
CS3_ECC_START
CS2_ECC_START
Reserved
RW -
RW -
RW -
RW -
5
4
3
2
1
0
4BIT_ECC_SEL
CS5_USE_NAND
CS4_USE_NAND
CS3_USE_NAND
CS2_USE_NAND
Table 4-9
NAND Flash Control Register (NANDFCR) Details (Part 1 of 2)
Bit
Field
Reset Value
Description
31-14
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect
13
ADDR_CALC_START
0x0
NAND Flash 4-bit ECC error address and error value calculation start.
Set to 1 to start 4-bit ECC error address and error value calculation on read syndrome.
This bit is cleared when any of the NAND Flash Error Address registers or NAND Flash
Error Value registers are read.
Writing a 0 has no effect.
12
4BIT_ECC_START
0x0
NAND Flash 4-bit ECC start for the selected chip select.
Set to 1 to start 4-bit ECC calculation on data for NAND Flash on chip select selected by
4BIT_ECC_SEL. This bit is cleared when any of the NAND Flash 4-Bit ECC registers are
read.
Writing a 0 has no effect.
11
CS5_ECC_START
0x0
NAND Flash 1-bit ECC start for chip select CE3.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE3. This bit is cleared
when NAND Flash CS5 1-Bit ECC register is read.
Writing a 0 has no effect.
10
CS4_ECC_START
0x0
NAND Flash 1-bit ECC start for chip select CE2.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE2. This bit is cleared
when NAND Flash CS4 1-Bit ECC register is read.
Writing a 0 has no effect.
9
CS3_ECC_START
0x0
NAND Flash 1-bit ECC start for chip select CE1.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE1. This bit is cleared
when NAND Flash CS3 1-Bit ECC register is read.
Writing a 0 has no effect.
8
CS2_ECC_START
0x0
NAND Flash 1-bit ECC start for chip select CE0.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE0. This bit is cleared
when NAND Flash CS2 (CE0) 1-Bit ECC register is read.
Writing a 0 has no effect.
7-6
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect