Texas Instruments EMIF16, Руководство пользователя

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2.5 ASRAM/NOR Flash Interface
2-8 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011
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Chapter 2—Architecture
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The read cycle as described above is shown in the Figure 2-4 . Refer to device datasheet
for timing characteristics.
Figure 2-4 Asynchronous Read Timing Diagram
2.5.4.2 Asynchronous Writes
An asynchronous write cycle proceeds as follows (see Note— 1, 2 below):
• At the start of the setup period:
– Setup, strobe and hold values are set according to the W_SETUP,
W_STROBE and W_HOLD values programmed in the Async 1/2/3/4 Config
Register
– EMIFCE becomes active, if not already active from a previous access.
– EMIFBE[1:0] become valid
– Address on address lines on EMIFA[23:0] become valid.
– Data on EMIFD[15:0] is driven
– EMIFRnW becomes active (LOW).
• At the start of the strobe period, EMIFWE becomes active.
• At the start of the hold period, EMIFWE becomes inactive.
• At the end of the hold period
– Address on address lines EMIFA[23:0] become invalid.
– EMIFD[15:0] becomes inactive.
– EMIFCE becomes inactive (if no additional read/write accesses to the same
chip select space are pending).
EMIFCE
EMIFBE[1:0]
EMIFA[23:0]
Byte enables
Address
Read data EMIFD[15:0]
EMIFOE
EMIFWE
EMIFRnW
Read setup Read strobe Read hold