Texas Instruments EMIF16, Руководство пользователя

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2.5 ASRAM/NOR Flash Interface
SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 2-9
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Chapter 2—Architecture
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Bus contention is addressed by having a programmable turnaround time inserted
between back-to-back accesses to the same or different CE spaces (See
Section 2.5.2 for
turnaround cycles).
Note—
1: In case an asynchronous request cannot be serviced in a single
asynchronous access cycle, multiple cycles are needed to complete the single
read or write request. In this case, the EMIF16 enters the setup phase directly
without incurring turnaround cycles.
Note—
2: If the entire read or write access has completed and there are more
requests pending, the EMIF16 enters turnaround state and waits for
programmed turnaround cycles.
Figure 2-5 shows a write cycle initiated as described above. Refer to the device datasheet
for timing characteristics.
Figure 2-5 Asynchronous Write Timing Diagram
2.5.5 Select Strobe Mode
The Select Strobe (SS) Mode is selected when the ‘ss’ bit in Async Wait Cycle Config
Register (AWCCR) is set to ‘1’. SS mode overrides the WE strobe mode when ‘ss’ = 1.
In SS mode, EMIFBE[1:0] act as byte enables. However the chip select EMIFCE behaves
as the strobe and is active only during the strobe period.
EMIFCE
EMIFBE[1:0]
EMIFA[23:0]
Byte enables
Address
Write data EMIFD[15:0 ]
EMIFOE
EMIFWE
EMIFRnW
Write setup Write strobe Write hold