PCLK
PDI
PSEL
Address
Read mode
6
5
4
3
2
1
0
T
SS
T
CL,min
T
CH,min
T
HS
R
PDO
7
6
5
4
3
2
1
0
Data byte
T
SH
SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
Figure 5-5. Configuration Registers Read Operation
Table 5-1. Serial Interface, Timing Specification
(1)
PARAMETER
MIN
MAX
UNIT
CONDITION
F
PCLK
PCLK, clock frequency
10
MHz
T
CL,min
PCLK low pulse duration
50
ns
The minimum time PCLK must be low.
T
CH,min
PCLK high pulse duration
50
ns
The minimum time PCLK must be high.
The minimum time PSEL must be low before
T
SS
PSEL setup time
25
ns
positive edge of PCLK.
The minimum time PSEL must be held low
T
HS
PSEL hold time
25
ns
after the negative edge of PCLK.
T
SH
PSEL high time
50
ns
The minimum time PSEL must be high.
The minimum time data on PDI must be ready
T
SD
PDI setup time
25
ns
before the positive edge of PCLK.
The minimum time data must be held at PDI,
T
HD
PDI hold time
25
ns
after the positive edge of PCLK.
T
rise
Rise time
100
ns
The maximum rise time for PCLK and PSEL
T
fall
Fall time
100
ns
The maximum fall time for PCLK and PSEL
(1)
The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is
valid for is 20 pF.
5.6
Signal Interface
The CC1020 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase-
level) encoded data. CC1020 can also synchronize the data from the demodulator and provide the data
clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register.
CC1020 can be configured for three different data formats: Synchronous NRZ mode, Transparent
Asynchronous UART mode, and Synchronous Manchester encoded mode.
Copyright © 2006–2015, Texas Instruments Incorporated
Detailed Description
21
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