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TABLE 70. ADC_ALC_1 (0x81h)
Bits
Field
Description
2:0
ADC_SAMPLE
This programs the timers on the ALC with the closest sample rate of the ADC.
ADC_SAMPLE
Expected ADC f
S
000
8kHz
001
12kHz
010
16kHz
011
24kHz
100
32kHz
101
48kHz
110
96kHz
111
192kHz
3
LIMITER
If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the
signal as soon as it reaches target and release it at the decay rate, once signal level reduces below
target. The I
2
C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC
will apply. Care should be taken when choosing the optimum I
2
C gain setting whenever enabling
the Limiter.
4
STEREO LINK
If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo
output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual
mono.
5
SOURCE_RSEL
If both SOURCE_OVR and this bit is set, the right ADC ALC channel will be active.
6
SOURCE_LSEL
If both SOURCE_OVR and this bit is set, the left ADC ALC channel will be active.
7
SOURCE_OVR
If set, the active channel of the ADC ALC is determined by SOURCE_RSEL and SOURCE_LSEL.
If cleared, the active channel of the ADC ALC is determined by the selected input to the ADC.
MONO enables left ALC, AUX enables right ALC, MIC enables left and / or right ALC depending
on which ADC channel MIC is selected to.
TABLE 71. ADC_ALC_2 (0x82h)
Bits
Field
Description
3:0
NOISE_FLOOR
This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from
the ALC to avoid noise pumping.
NOISE_FLOOR
Noise Floor (dB)
0000
–39
0001
–42
0010
–45
0011
–48
0100
–51
0101
–54
0110
–57
0111
–60
1000
–63
1001
–66
1010
–69
1011
–72
1100
–75
1101
–78
1110
–81
1111
–84
4
NG_ENB
This enables the Noise Gate.
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LM49360
Содержание Boomer LM49360
Страница 3: ...5 0 LM49360 Overview 301282h8 FIGURE 1 LM49360 Block Diagram www ti com 2 LM49360...
Страница 4: ...6 0 Typical Application 30128211 FIGURE 2 Sub PMU System Diagram 3 www ti com LM49360...
Страница 5: ...30128216 FIGURE 3 AP PMU System Diagram www ti com 4 LM49360...
Страница 16: ...301282h9 FIGURE 4 PMU State Machine 15 www ti com LM49360...
Страница 68: ...30128213 FIGURE 20 Internal Clock Network 67 www ti com LM49360...
Страница 89: ...301282i1 FIGURE 28 Timing for I2S Master 301282i2 FIGURE 29 Timing for I2S Slave www ti com 88 LM49360...
Страница 128: ...40 0 Schematic Diagram 30128220 FIGURE 36 Demo Board Schematic 127 www ti com LM49360...
Страница 129: ...30128245 FIGURE 37 Demo Board Schematic www ti com 128 LM49360...
Страница 130: ...41 0 Demonstration Board Layout 30128243 FIGURE 38 Top Silkscreen 30128244 FIGURE 39 Top Layer 129 www ti com LM49360...
Страница 131: ...30128238 FIGURE 40 Inner Layer 2 30128239 FIGURE 41 Inner Layer 3 www ti com 130 LM49360...
Страница 132: ...30128240 FIGURE 42 Inner Layer 4 30128241 FIGURE 43 Inner Layer 5 131 www ti com LM49360...
Страница 133: ...30128231 FIGURE 44 Bottom Layer 30128242 FIGURE 45 Bottom Silkscreen www ti com 132 LM49360...
Страница 136: ...Notes 135 www ti com LM49360...