Texas Instruments Boomer LM49360, Руководство пользователя

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30.0 LM49360 Clock Network
(Refer to Figure 20 )
The audio DAC and ADC operate at a clock frequency of 2*OSR*f
S
where OSR is the oversampling ratio and f
S
is the sampling
frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC can operate at two
different OSR settings (128, 125). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for
48kHz data. If a 12.288MHz clock is not available, then the internal PLL can be used to generate the desired clock frequency.
Otherwise, if a 12.288MHz is available, the PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC
clock divider can also be used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider
could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.
The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input,
the PORT1_CLK input, the PORT2_CLK input, or PLL output.
For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to the PLL can come
from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.
The LM49360's Power Management Circuit (PMC) requires a clock of
≈
300kHz that is independent from the DAC or ADC. The
PMC clock divider is available to generate the correct clock to the PMC block. The PMC clock path can be driven directly by the
MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK.
TABLE 30. DAC Clock Requirements
DAC Sample Rate
(kHz)
Clock Required at A
(OSR = 128)
Clock Required at A
(OSR = 125)
Clock Required at A
(OSR = 64)
8 2.048 MHz 2 MHz 1.024 MHz
11.025 2.8224 MHz 2.75625 MHz 1.4112 MHz
12 3.072 MHz 3 MHz 1.536 MHz
16 4.096 MHz 4 MHz 2.048 MHz
22.05 5.6448 MHz 5.5125 MHz 2.8224 MHz
24 6.144 MHz 6 MHz 3.072 MHz
32 8.192 MHz 8 MHz 4.096 MHz
44.1 11.2896 MHz 11.025 MHz 5.6448 MHz
48 12.288 MHz 12 MHz 6.144 MHz
96 24.576 MHz 24 MHz 12.288 MHz
TABLE 31. ADC Clock Requirements
ADC Sample Rate
(kHz)
Clock Required at B
(OSR = 128)
Clock Required at B
(OSR = 125)
8 2.048 MHz 2 MHz
11.025 2.8224 MHz 2.75625 MHz
12 3.072 MHz 3 MHz
16 4.096 MHz 4 MHz
22.05 5.6448 MHz 5.5125 MHz
24 6.144 MHz 6 MHz
32 8.192 MHz 8 MHz
44.1 11.2896 MHz 11.025 MHz
48 12.288 MHz 12 MHz
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LM49360