Texas Instruments Boomer LM49360, Руководство пользователя

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8.2 AUDIO PMC STATE MACHINE DESCRIPTION
The basic premise of the audio section is that it should be
configured in shutdown and enabled via the ENABLE register
in 0x00h bit[0]. Once it has been enabled the CHIP_ACTIVE
bit is set in 0x00h bit[7]. To disable the device the user should
clear the ENABLE bit (0x00h bit[0]) and wait for the CHIP_AC-
TIVE(0x00h bit [7]) bit to clear before re-enabling the device.
Sufficient time must be given for the state transitions to com-
plete before issuing another command via I
2 C. A device en-
able command takes 8.5k clock cycles (typically 25ms) for the
device to reach the ON state. A command to disable the de-
vice takes 0.75k clock cycles (2.2ms) to reach the OFF state.
The stated times are based on using the low power internal
oscillator, which is typically 350kHz but can vary by as much
as 30%.
The ENABLE bit drives a sequencer that is responsible for
controlling bias circuits, clocking, click and pop and clean op-
eration of the volume controls without requiring manual I
2 C
commands, a simplified overview is shown below:
30128259
FIGURE 5. LM49360 Audio PMC Sequencer Overview with Typical Timing.
The Finite State Machine (FSM) can be clocked from a divid-
ed down MCLK, an I
2 S PORT or an internal 350kHz oscillator.
The device will automatically control the internal clock gating
of the MCLK and Oscillator clocks. The I
2 S clock inputs are
not automatically gated to allow to digital bypass modes when
the analog codec circuits are disabled. The FSM can be
clocked faster if required - the maximum clock speed to the
PMC is 14MHz.
The user can use the internal oscillator for the PMC and it will
only enable the oscillator when required (the low power os-
cillator is reused by many circuits in the device that require
delays, the PMC controls when it should be enabled). If the
PMC is not using the oscillator (i.e. PMC_CLK_SEL is set to
MCLK) it will remain off unless another circuit requires it. The
PMC will also automatically control the MCLK input buffer to
reduce power on chip but the power spent driving the PCB
trace to the MCLK pin makes the oscillator the preferred so-
lution. The only advantage to using an external pin is where
precise timing of the sequencer is needed. When an external
clock is required it should not be removed until the device has
reached the OFF condition. The function and timing of each
stage is detailed below:
8.2.1 State_0 (OFF)
In this state the internal clocks and oscillators are disabled
(unless an OVR bit in register 0x00 is set). The device is un-
biased and only leakage current is drawn from the supplies.
The I
2 C port is controllable and all control registers are free
to be changed.
When the ENABLE bit is set the device enables either the
MCLK pad or low power oscillator and waits 2 clock cycles
before rechecking the ENABLE bit. If it is still set the device
proceeds to STATE_1, otherwise the device remains in
STATE_0 and the deglitching digital flip-flops are disabled
and reset.
8.2.2 State_1 (BIAS)
In state 1 the device enables its internal references and com-
mon mode points. The preamplifiers to analog inputs are
enabled and the PMC starts to inject current into decoupling
caps. The PMC clock is started and the clocking circuits are
readied. The mixer and amplifiers remain muted.
The device waits 8192 clock cycles (typically 23 to 24ms using
the internal oscillator, enough time for the common mode
points to reach vcm and start to settle without any audible click
and pop or coupling back to driving circuits) before moving to
the next stage.
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LM49360