Texas Instruments Boomer LM49360, Руководство пользователя

Страница: 13 / 137

Pin Descriptions
Pin Pin Name Type Direction Description
A1 VINL1 Supply Input Input for LDO1 and LDO2
A2 LDO3 Supply Output LDO3 Output
A3 OVR Digital Input
OVR allows hardware override of the enabling of LDO1 thru LDO7, Buck 1 and Buck
2. The OVR control is enabled in the OVR and ENB2 registers. When bits in these
registers are set, a high on OVR enables the corresponding voltage source. If
CONFIG pin is high, the Bank 1 OVR register has LDO4_OVR bit set, via the
EEPROM after power-up, allowing OVR enabling of LDO4. The functionality of OVR
override is available in all modes (ie CONFIG pin L, H or Z). The OVR pin has an
internal 500K
Ω
pull-down resistor.
A4 LDO5 Supply Output LDO5 Output
A5 VINL3 Supply Input Inputs for LDO5, LDO6, LDO7(HILO)
A6 PGND Supply Input PMU and LDO ground
A7 PS_HOLD/SUBOVR Digital Input
CONFIG = Low: In AP_PMU mode, PS_HOLD is a power control input from an
external processor. CONFIG = High or High Z: In sub-PMU mode, setting the
SUBOVR/(BUCK2_EN) pin high enables BUCK2 and any combination of LDO1, 4,
5, 7 or Buck 1 that has its SUBOVR I
2 C register bit set to 1. In this configuration the
SUBOVR(BUCK2_EN) pin has an internal 500k
Ω
pull-down resistor.
A8
μ
PWR
Supply Input
Filter point for internal
μ
PWR LDO
B1 LDO1 Supply Output LDO1 Output
B2 LDO2 Supply Output LDO2 Output
B3 VINL2 Supply Input Input for LDO3 and LDO4
B4 LDO4 Supply Output LDO4 Output
B5 LDO6 Supply Output LDO6 Output
B6 LDO7 Supply Output
LDO7 low current output used primarily for powering an external module's standby
power input.
B7 PWR_ON / EN Supply Input
CONFIG = Low: In AP-PMU mode, PWR_ON = low enables standby mode and
PWR_ON = high turns on the BUCK and LDO outputs. The PWR_ON pin expects
to be driven by Vbatt via an external switch. CONFIG = High or High Z: In sub-PMU
mode EN = low enables standby mode and EN = high turns on the BUCK and LDO
outputs. The EN pin expects to be driven by an external processor. PWR_ON/EN
has an internal 500k
Ω
pull-down resistor.
B8 RESET_N / GPO Digital Output
RESET_N is an open drain output that indicates that the BUCK and LDO supplies
are stable. This pin can also be programmed as a general purpose output, GPO, in
sub-PMU mode when CONFIG = High or High Z.
C1 HPR Analog Output Headphone right output
C2
A_V
DD
Supply Input
DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog mixer (AUX and
class D), and Earpiece amplifier power supply input
C3 AGND Supply Input
DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog mixer (AUX and
class D), and Earpiece amplifier ground
C4 DAC REF Analog Input/Output Filter point for the DAC reference
C5 ADC REF Analog Input
Filter point for the ADC reference. Connect this pin to A_V
DD
.
C6 SDA Digital Input/Output I
2 C interface data line
C7 CONFIG Supply Input
Hardwire to DGND for Bank 2 AP-PMU operation. Hardwire to Vbatt for Bank 1 sub-
PMU operation. Leave floating for Bank 0 sub-PMU operation.
C8 DGND Supply Input Reserved pin, connect to DGND
D1 HPL Analog Output Headphone left output
D2 AUX_R/AUX+ Analog Input Right analog input or positive differential auxiliary input
D3 AUX_L/AUX- Analog Input Left analog input or negative differential auxiliary input
D4 PORT2_SYNC Digital Input/Output Audio Port 2 sync signal (can be master or slave)
D5 PORT2_SDI Digital Input Audio Port 2 serial data input
www.ti.com 12
LM49360