LMZ10500
www.ti.com
SNVS723C – OCTOBER 2011 – REVISED MARCH 2013
OVERVIEW
The LMZ10500 SIMPLE SWITCHER® nano module is an easy-to-use step-down DC-DC solution capable of
driving up to 650mA load in space-constrained applications. Only an input capacitor, an output capacitor, a small
V
CON
filter capacitor, and two resistors are required for basic operation. The nano module comes in 8-pin POS
footprint package with an integrated inductor. The LMZ10500 operates in fixed 2.0MHz PWM (Pulse Width
Modulation) mode, and is designed to deliver power at maximum efficiency. The output voltage is typically set by
using a resistive divider between the built-in reference voltage V
REF
and the control pin V
CON
. The V
CON
pin is the
positive input to the error amplifier. The output voltage of the LMZ10500 can also be dynamically adjusted
between 0.6V and 3.6V by driving the V
CON
pin externally. Internal current limit based softstart function, current
overload protection, and thermal shutdown are also provided.
CIRCUIT OPERATION
The LMZ10500 is a synchronous Buck power module using a PFET for the high side switch and an NFET for the
synchronous rectifier switch. The output voltage is regulated by modulating the PFET switch on-time. The circuit
generates a duty-cycle modulated rectangular signal. The rectangular signal is averaged using a low pass filter
formed by the integrated inductor and an output capacitor. The output voltage is equal to the average of the duty-
cycle modulated rectangular signal. In PWM mode, the switching frequency is constant. The energy per cycle to
the load is controlled by modulating the PFET on-time, which controls the peak inductor current. In current mode
control architecture, the inductor current is compared with the slope compensated output of the error amplifier. At
the rising edge of the clock, the PFET is turned ON, ramping up the inductor current with a slope of (V
IN
-
V
OUT
)/L. The PFET is ON until the current signal equals the error signal. Then the PFET is turned OFF and
NFET is turned ON, ramping down the inductor current with a slope of V
OUT
/L. At the next rising edge of the
clock, the cycle repeats. An increase of load pulls the output voltage down, resulting in an increase of the error
signal. As the error signal goes up, the peak inductor current is increased, elevating the average inductor current
and responding to the heavier load. To ensure stability, a slope compensation ramp is subtracted from the error
signal and internal loop compensation is provided.
INPUT UNDER VOLTAGE DETECTION
The LMZ10500 implements an under voltage lock out (UVLO) circuit to ensure proper operation during startup,
shutdown and input supply brownout conditions. The circuit monitors the voltage at the V
IN
pin to ensure that
sufficient voltage is present to bias the regulator. If the under voltage threshold is not met, all functions of the
controller are disabled and the controller remains in a low power standby state.
SHUTDOWN MODE
To shutdown the LMZ10500, pull the EN pin low (<0.5V). In the shutdown mode all internal circuits are turned
OFF.
EN PIN OPERATION
The EN pin is internally pulled up to V
IN
through a 790k
Ω
(typ.) resistor. This allows the nano module to be
enabled by default when the EN pin is left floating. In such cases V
IN
will set EN high when V
IN
reaches 1.2V. As
the input voltage continues to rise, operation will start once V
IN
exceeds the under-voltage lockout (UVLO)
threshold. To set EN high externally, pull it up to 1.2V or higher. Note that the voltage on EN must remain at less
than VIN+ 0.2V due to absolute maximum ratings of the device.
INTERNAL SYNCHRONOUS RECTIFICATION
The LMZ10500 uses an internal NFET as a synchronous rectifier to minimize the switch voltage drop and
increase efficiency. The NFET is designed to conduct through its intrinsic body diode during the built-in dead time
between the PFET on-time and the NFET on-time. This eliminates the need for an external diode. The dead time
between the PFET and NFET connection prevents shoot through current from V
IN
to PGND during the switching
transitions.
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