LED0:
By default, this pin indicates that link is established. Additional functionality is configurable via
LEDCR1[3:0] register bits in the DP83867 device and LEDS_CFG1[3:0] register bits in the DP83869 device.
LDE0 is not used in the CPSW PHY (DP83867), this is also a strap pin which is used to set mirror enable. Since
these features are not required the strapping for the LED0 is not provided. In the DP83869 ICSSG PHY the
LED0 is connected to PRG1_PRU1_GPO8 & PRG1_PRU0_GPO8 of SoC for link status. This pin is also a strap
pin which is having internal pulldown resistor to set Auto Negotiation Disable option in the DP83869 device. The
default condition is to auto negotiate and advertise link as 10/100/1000Mbps
LED_1
: By default, this pin indicates that 1000BASE-T link is established. This setting can be changed to
Auto negotiate to 10/100Mbps using the strap resistors. Additional functionality is configurable via LEDCR1[7:4]
register bits in the DP83867 device and LEDS_CFG1[7:4] register bits in the DP83869 device. LED_1 is a also
an strap pin which is having internal pulldown resistor to set RGMII TX Clock Skew in the DP83867 device and
to select Auto Negotiation mode in the DP83869 device. Since this pin will be set to active on both the devices
this would result in dim LED lighting when LED is driven directly. So a MOSFET is used to drive LED as shown
in
LED_2
: By default, this pin indicates receive or transmit activity. Additional functionality is configurable via
LEDCR1[11:18] register bits in the DP83867 device and LEDS_CFG1[11:18] register bits in the DP83869 device.
LED_2 is also a strap pin, which is having internal pulldown resistor to set RGMII TX Clock Skew in the
DP83867 device and to select Auto Negotiation mode in the DP83869 device. The default condition is to auto
negotiate and advertise link as 10/100/1000Mbps, this can be changed using the strap resistors provided. The
pull up resistor used for strap setting results in dim LED lighting when LED is driven directly. So a MOSFET is
used to drive LED .
GPIO1
: In the DP83867 PHY, the GPIO can be configured to function as LED3 through GPIO Mux Control
Register 1 (GPIO_MUX_CTRL1) and the LED configuration can be set by programming LEDCR1 register this is
also a strap pin which is used to set fast link drop (FDP), currently this is disabled. In the DP83869 PHY The
GPIO can be configured to function as LED_GPIO(3) through GPIO Mux Control Register (GPIO_MUX_CTRL)
and the LED configuration can be set by programming LEDS_CFG1 register, this is also a strap pin which is
used to select RGMII to copper mode of operation on startup. This can be changed to MII mode using the MDC
&MDIO pin to update the GEN_CFG1 register – 0x9 (gigabit ethernet advertising should be disabled when using
MII mode as the PHY would not link up at 1000Mbps speed)
RJ45 Connector LED Indication -CPSW (DP83867):
LED1 and GPIO1 is connected to dual LEDs of RJ45 to indicate 10/100 or 1000MHz link. Orange LED indicates
10/100 speed and Green LED is to indicate 1000MHz speed
LED2 is connected to RJ45 LED (Yellow) to indicate transmit/receive activity.
RJ45 Connector LED Indication -ICSSG (DP83869):
LED1 is connected to RJ45 LED (Green) to indicate 1000MHz speed
LED2 is connected to RJ45 LED (Yellow) to indicate transmit/receive activity.
System Description
SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021
AM64x GP EVM User's Guide
35
Copyright © 2021 Texas Instruments Incorporated
