Alternate Hardware Configurations
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5
Alternate Hardware Configurations
This section describes alternate hardware configurations in order to achieve better results or to more
closely mimic the system configuration.
5.1
Clocking Options
The default clocking mode uses the LMK04828 to generate the ADC sampling clock and FPGA clocks.
There are three additional clocking options that the EVM supports. These options are described in
sections
Section 5.1.1
through
Section 5.1.3
:
5.1.1
External ADC Sampling Clock
An external clock can be used as the sampling clock for the ADC. This clock can be provided through a
transformer using the
EXT_ADC_CLK
connector (J6). For this option C47 and C48 need to be uninstalled
and installed at R35 and R39. The LMK04828 must still be used to provide the device clock to the
TSW14J56 and the SYSREF signals to both boards. This option will provide the best performance as long
as the clock source has better phase-noise performance than the LMK04828. The source of the EXT ADC
clock must be synchronized with the LMK04828. To accomplish this, send the 10-MHz reference output
from the signal generator and connect it to J12 (CLKIN) of the ADS5XJ6XEVM. This will cause LED D6 to
illuminate indicating the LMK VCXO source is locked to the external reference clock. The provided LMK
configuration files will work in this mode as well. To turn off the ADC clock provided by the LMK04828 to
reduce switching noise, click on the LMK04828 tab, then click on clock outputs tab, then select
“Powerdown” for
DCLK Type
under
Clock Out 2 and 3
, as shown in
Figure 9
.
Figure 9. Low Level View Tab
14
ADS5XJ6X Evaluation Module
SLAU641D – June 2015 – Revised January 2016
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