High-pass
Filter
Diode Clamp
Low-pass Filter
Input Signal
Connector
DB Connector for
10 ECG Electrodes
JP26-
JP33
JP3
JP6 to
J14
JP18
J4
J1
Shield
Drive
Power
Mgmt
Power
Connector
External
Clock
(optional)
External
Reference
(optional)
ADS1298R
ECG SOC
MMB0/C5505 Interface
Connectors
ADS1298R Signals
Connectors
ADS1298REVM
3 Limb and
6 Chest
Electrodes
Right Leg
Electrodes
Shield
ADS1298R Daughter Card Hardware Details
46
SBAU181B – March 2011 – Revised Janurary 2016
Copyright © 2011–2016, Texas Instruments Incorporated
ADS1298R
6
ADS1298R Daughter Card Hardware Details
The ADS1298RECG front-end evaluation board is configured to be used with the TI MMB0 data converter
evaluation platform. The ADS1298RECG-FE board is a four-layer circuit board. The board schematic and
layout are provided in
The ADS1298R can be used as a demonstration board for standard, 12-lead ECG applications with an
input configuration of 10 electrodes. Users can also bypass the 12-lead configuration and provide any type
of signal directly to the ADS1298R through a variety of hardware jumper settings (JP26-JP33; see
). External support circuits are provided for testing purposes such as external references,
clocks, lead-off resistors, and shield drive amplifiers.
shows the functional block diagram with important jumper names for the EVM.
Figure 41. ADS1298R Front-End Block Diagram
6.1
Jumper Description
shows the jumpers on the ADS1298RECG-FE and options available for each jumper.
(1)
Requires installation of JP25 and references U3/U4
Table 5. ADS1298RECG-FE Default Jumper/Switch Configuration
Jumper
Function
Settings
JP1
Installed
RLD feedback
JP2
AVDD supply source
1-2: AVDD selected for bipolar supply operation (AVDD = +2.5V)
2-3: AVDD selected for single supply operation (AVDD = +3.0V)
JP3
External Reference Connection
(Header Not Installed)
(1)
Open: External reference not connected
Installed: External reference connected
JP4
Connect EVM +5V rail to
J4(power header)
Open: EVM +5V must be supplied externally
Installed: EVM +5V supplied from J4 (power header)
JP5
PWDN source
Open: PWDN pin controlled from J5 header (pulled up to DVDD)
Installed: Device is powered down (PWDN pin = AGND)
JP6 to
JP114
Input signal DC/AC couples
(Header Not Installed)
1-2: DC-coupled input signals (Pins 1-2 shorted on PCB)
2-3: AC-coupled input signals (Requires installation of header and cutting PCB
short of pin 1-2)
JP15
ECG shield drive connected
1-2: ECG shield is grounded (AGND)
2-3: ECG shield is connected to buffer (required U2 installation, otherwise shield
connection is open)
JP16
Wilson Central Terminal (
WCT
)
connection
Open:
WCT
NOT connected to JP26-30 and JP33
Installed:
WCT
connected to JP26-30 and JP33 for connection to CH1 and CH4-8
IN-