2 Introduction
This design is developed for the Alpha Data System Development Kit (SDEV) to interface with the
ADC12DJ3200EVMCVAL using JMODE0. This design uses custom TI JESD204B IP, which implements both
JESD204B Base IP and JESD204B PHY IP to get JESD204B data from the ADC12DJ3200QML-SP device at
6.2 GSPS in single-device mode with 12.4 Gbps data lane rate. The reference design implements a transport
layer that collects 40 samples from the 8 lanes (as depicted in the JMODE0 table of the data sheet). The
samples are captured using the Xilinx Internal Logic Analyzer (ILA) tool and offloaded to a PC were the results
can be displayed using the TI
High-Speed Data Converter Pro GUI
.
3 Functionality
The AlphaData SDEV has a standard FMC+ connector that provides an interface between this board and the TI
JESD204B ADC12DJ3200CEVMCVAL. For communicating, the AlphaData SDEV uses JTAG to acquire and
receive data using a host PC. The industry-standard JTAG connector is used for configuring the FPGA using the
Vivado
®
Design Suite, a design tool by Xilinx. The firmware designed for this integration only supports JMODE0
at 6.2 GSPS single ADC. Future firmware will support all modes of this ADC.
Introduction
SLAU833A – MAY 2020 – REVISED OCTOBER 2020
ADC12DJ3200EVMCVAL With Alpha Data Xilinx
®
Kintex Ultrascale Space
Development Kit
3
Copyright © 2020 Texas Instruments Incorporated
