7 Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions
This chapter provides descriptions to program the ADC12DJ3200EVM, program the FPGA, setup the
ADC12DJ3200EVM for manual SYNC operation, capture the data with the FPGA, then view the captured data
with the HSDC Pro GUI.
7.1 Configure the ADC EVM
Use the following steps to configure the ADC EVM.
1. Open ADC12DJ3200EVM-CVAL GUI, choose Fclk = 3100MHz and select JMODE0 (equivalent to 6.2 GSPS
ADC sample rate and 12.4Gbps lane rate) in the EVM tab.
2. Click “Program Clocks and ADC”. On the ADC EVM, verify PLL1 LCKD LED turns on. This will indicate the
LMK04828 PLL1 is locked to the onboard 100-MHz VCXO.
3.
Figure 7-1. ADC12DJ3200EVM-CVAL GUI
Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions
SLAU833A – MAY 2020 – REVISED OCTOBER 2020
ADC12DJ3200EVMCVAL With Alpha Data Xilinx
®
Kintex Ultrascale Space
Development Kit
11
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