Texas Instruments ADC12DJ3200CVAL, Руководство пользователя

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6 Hardware Setup
This section provides directions and illustrations for setting up the hardware.
Figure 6-1. ADC12DJ3200EVM Board
By default, the FMC+ interface EEPROM on the ADC12DJ3200EVM is installed. Without this part, the
FMC3_VADJ voltage for the FPGA bank that drives the JESD204B SYNC will be set to 0 V, thus preventing the
SYNC signal from working. Using the ADC manual SYNC is a work around for this. U5 (24C65T-I/SM from
Microchip) is programmed with the provided .bin file called "FMC-ADC12DJ3200-CVAL.bin". This .bin file uses
address 0x53 which is required for the FMC+ slot on the Alpha Data board and will set the FMC3_VADJ to 1.8 V
after power up. With the EEPROM installed and programmed properly, after power up, test point TP3 on the
Alpha Data board should be at 1.8 V.
1. Connect the Alpha Data board with ADC12DJ3200 CVAL EVM. Use the FMC+ connector (J3) to connect the
ADC EVM.
2. Connect the output power cable from the CX 650 power supply to the Alpha Data board as Figure 6-2 shows:
www.ti.com Hardware Setup
SLAU833A – MAY 2020 – REVISED OCTOBER 2020
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ADC12DJ3200EVMCVAL With Alpha Data Xilinx ® Kintex Ultrascale Space
Development Kit
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