Texas Instruments ADC12DJ3200CVAL, Руководство пользователя

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2. Implement the following steps (in order):
• Click on the "JESD Block Enable" to disable it (the green arrow should not be lit).
• Click on the SFORMAT button (to enable it). The FPGA firmware is using unsigned data and a K value of
4.
• Click the JSYNC_N Sync _Request button (it should be enabled or ‘lit’).
• Select “No SYNC Input Signal” from the SYNC Input Selection drop-down menu.
Figure 7-4. Setting ADC to use Software SYNC
www.ti.com Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions
SLAU833A – MAY 2020 – REVISED OCTOBER 2020
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ADC12DJ3200EVMCVAL With Alpha Data Xilinx ® Kintex Ultrascale Space
Development Kit
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