TPMC810 User Manual Issue 2.0.0
Page 9 of 22
4 Addressing
4.1 PCI Configuration space
PCI CFG
Register
Address
Write ‘0’ to all unused (Reserved) bits
PCI
writeable
Initial Values
(Hex Values)
31 24
23 16
15 8
7 0
0x00
Device ID
Vendor ID
N
032A 1498
0x04
Status
Command
Y
0280 0000
0x08
Class Code
Revision ID
N
028000 00
0x0C
not supported
Header Type
not supported
not supported
Y[7:0]
00 00 00 00
0x10
PCI Base Address 0 for MEM Mapped Config. Registers
Y
FFFFFF80
0x14
PCI Base Address 1 for I/O Mapped Config. Registers
Y
FFFFFF81
0x18
PCI Base Address 2 for Local Address Space 0
Y
FFFFFE00
0x1C
not supported
Y
00000000
0x20
not supported
Y
00000000
0x24
not supported
Y
00000000
0x28
not supported
N
00000000
0x2C
Subsystem ID
Subsystem Vendor ID
N
000A 1498
0x30
not supported
Y
00000000
0x34
Reserved
Cap. Ptr.
N
000000 40
0x38
Reserved
N
00000000
0x3C
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Y[7:0]
00 00 01 00
0x40-
0xFF
Reserved
00000000
Table 4-1 : PCI Controller Header
4.2 PCI Address Space Overview
PCI
BAR
PCI Base Address
(Offset in PCI
Configuration
Space)
PCI
Space
Mapping
Size
(Byte)
Port
Width
(Bit)
Endian
Mode
Description
0
2 (0x18)
MEM
512
8
BIG
CAN Controller
Address Space
1
3 (0x1C)
-
-
-
-
Not Used
2
4 (0x20)
-
-
-
-
Not Used
3
5 (0x24)
-
-
-
-
Not Used
Table 4-2 : PCI Address Space Overview
