TPMC810 User Manual Issue 2.0.0
Page 15 of 22
5 Programming Hints
5.1 SJA1000 CAN Controller
5.1.1 SJA1000 CAN Controller
The SJA1000 clock input frequency is 16 MHz (for both SJA1000 controllers).
See chapter “SJA1000 CAN Controller Registers” for an overview of all registers in the different
modes. Note that some registers are available in PeliCAN Mode only and that the Control Register is
available in BasicCAN Mode only. Furthermore some registers are read only or write only and some
can be accessed during Reset Mode only.
A transmit message has to be written to the transmit buffer. After a successful reception the
microprocessor may read the received message from the receive buffer and then release it for further
use.
5.1.2 Operating Modes
For register access, two different modes have to be distinguished:
Reset Mode
Operating Mode
The Reset Mode (see SJA1000 Control Register (CR; 0x0) for BasicCAN or Mode Register (MOD;
0x0) for PeliCAN, bit Reset Request) is entered automatically after a hardware-reset or when the
controller enters the bus-off state (see Status Register, bit Bus Status).
The operating mode is activated by resetting of the reset request bit in the control register.
5.1.3 Hardware Related Configuration Registers
The SJA1000 Output Control Register and Clock Divider Register have to be programmed as follows
(SJA1000 controller must be in Reset Mode):
Bit
Symbol
Description
7
OCTP1
11 : Push-Pull output stage
6
OCTN1
5
OCPOL1
0 :
Normal polarity
4
OCTP0
11 : Push-Pull output stage
3
OCTN0
2
OCPOL0
0 :
Normal polarity
1
OCMODE1
01 : Test output mode (bit reflection)
10 : Normal output mode
0
OCMODE0
Table 5-1 : Output Control Register (OCR; 0x08)
