TPMC671 User Manual Issue 1.1
Page 24 of 28
6 Configuration Hints
6.1 Software Reset (Controller and LRESET#)
A host on the PCI bus can set the software reset bit in the Miscellaneous Control Register (CNTRL;
0x50) of the PCI Controller PCI9030 to reset the Controller and assert LRESET# output. The PCI9030
remains in this reset condition until the PCI host clears the software reset bit.
6.2 Big / Little Endian
•
PCI – Bus ( Little Endian )
Byte 0
AD[7..0]
Byte 1
AD[15..8]
Byte 2
AD[23..16]
Byte 3
AD[31..24]
•
Every Local Address Space (0...3) and the Expansion ROM Space can programmed to operate in
Big or Little Endian Mode.
Big Endian
Little Endian
32 Bit
32 Bit
Byte 0
D[31..24]
Byte 0
D[7..0]
Byte 1
D[23..16]
Byte 1
D[15..8]
Byte 2
D[15..8]
Byte 2
D[23..16]
Byte 3
D[7..0]
Byte 3
D[31..24]
16 Bit upper lane
16 Bit
Byte 0
D[31..24]
Byte 0
D[7..0]
Byte 1
D[23..16]
Byte 1
D[15..8]
16 Bit lower lane
Byte 0
D[15..8]
Byte 1
D[7..0]
8 Bit upper lane
8 Bit
Byte 0
D[31..24]
Byte 0
D[7..0]
8 Bit lower lane
Byte 0
D[7..0]
Figure 6-1 : Local Bus Little/Big Endian
