TPMC671 User Manual Issue 1.1
Page 12 of 28
4.2.3 Control / Status Register
The Control / Status Register is a read/write register.
Bit
Symbol
Description
Access
Reset
Value
15 : 4
-
Not used and undefined during reads
- -
3 WD_STA
Watchdog Status Flag
1 = indicates that the watchdog had
recognized a failure and had disabled
all output channels. Also the Output
Register is locked.
0 = clears this bit and unlocks Output
Register
R/W 0
2 DB_ENA
Debounce Enable
1 = enables the debounce function for all
16 inputs
0 = disables debounce function
R/W 0
1 WD_ENA
Watchdog Enable
1 = enables watchdog for all 16 outputs
0 = disables watchdog function
R/W 0
0 INT_ENA
Global Interrupt Enable
1 = globally enables interrupt for all 16
inputs
0 = globally disables interrupts
The input channels generate interrupts
at pin INTA# of the PCI bus.
R/W 0
Figure 4-5 : Control / Status Register
Additional to this Global Interrupt Enable the Interrupt INTA# must be enabled in the PCI
Interrupt Line Register (PCIILR; 0x3C) of the PCI Controller PCI9030. Default after power-on and
reset is: INTA# is enabled.
The watchdog status is only active if the watchdog is enabled.
