TPMC671 User Manual Issue 1.1
Page 9 of 28
4 Local Space Addressing
4.1 PCI9030 Local Space Configuration
The local on board addressable regions are accessed from the PCI side by using the PCI9030 local
spaces.
PCI9030
Local
Space
PCI9030
PCI Base Address
(Offset in PCI
Configuration
Space)
PCI
Space
Mapping
Size
(Byte)
Port
Width
(Bit)
Endian
Mode
Description
0
2 (0x18)
IO
16
16
BIG
Local Register Space
1
3 (0x1C)
-
-
-
-
Not Used
2
4 (0x20)
-
-
-
-
Not Used
3
5 (0x24)
-
-
-
-
Not Used
Figure 4-1 : PCI9030 Local Space Configuration
4.2 Local Register Space Address Map
PCI Base Address:
PCI9030 PCI Base Address 2 (Offset 0x18 in PCI Configuration Space).
Offset to PCI
Base Address 2
Register Name
Size
(Bit)
0x00
Data Output Register
16
0x02
Data Input Register
16
0x04
Control / Status Register
16
0x06
Rising Edge Interrupt Enable Register
16
0x08
Falling Edge Interrupt Enable Register
16
0x0A
Rising Edge Interrupt Status Register
16
0x0C
Falling Edge Interrupt Status Register
16
0x0E
Debounce Time Register
16
Figure 4-2 : FPGA Register Space
