Tews Technologies TPMC671, Руководство пользователя

Страница: 4 / 28

TPMC671 User Manual Issue 1.1 Page 4 of 28
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................5
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................6
FIGURE 3-1 : ISOLATED DIGITAL OUTPUTS.................................................................................................7
FIGURE 4-1 : PCI9030 LOCAL SPACE CONFIGURATION ............................................................................9
FIGURE 4-2 : FPGA REGISTER SPACE .........................................................................................................9
FIGURE 4-3 : DATA OUTPUT REGISTER.....................................................................................................10
FIGURE 4-4 : DATA INPUT REGISTER.........................................................................................................11
FIGURE 4-5 : CONTROL / STATUS REGISTER ...........................................................................................12
FIGURE 4-6 : RISING EDGE INTERRUPT ENABLE REGISTER..................................................................13
FIGURE 4-7 : FALLING EDGE INTERRUPT ENABLE REGISTER ...............................................................14
FIGURE 4-8 : RISING EDGE INTERRUPT STATUS REGISTER..................................................................15
FIGURE 4-9 : FALLING EDGE INTERRUPT STATUS REGISTER ...............................................................16
FIGURE 4-10: DEBOUNCE TIME REGISTER ................................................................................................17
FIGURE 4-11: FORMULAS TO DETERMINE PRELOAD VALUE ..................................................................17
FIGURE 4-12: DEBOUNCE TIME / EXAMPLES .............................................................................................18
FIGURE 5-1 : PCI9030 HEADER....................................................................................................................19
FIGURE 5-2 : PCI9030 PLD BASE ADDRESS USAGE .................................................................................20
FIGURE 5-3 : PCI9030 LOCAL CONFIGURATION REGISTER ....................................................................21
FIGURE 5-4 : CONFIGURATION EEPROM TPMC671-XX ...........................................................................22
FIGURE 6-1 : LOCAL BUS LITTLE/BIG ENDIAN...........................................................................................24
FIGURE 7-1 : INPUT WIRING.........................................................................................................................26
FIGURE 7-2 : OUTPUT WIRING HIGH SIDE SWITCH..................................................................................26
FIGURE 7-3 : OUTPUT WIRING LOW SIDE SWITCH ..................................................................................26
FIGURE 8-1 : PIN ASSIGNMENT I/O HD68 SCSI-3 TYPE CONNECTOR ...................................................27
FIGURE 8-2 : MEZZANINE CARD CONNECTOR P14 ..................................................................................28