TMPE627 User Manual Issue 1.0.2
Page 31 of 34
8 Appendix A
This appendix contains the signal to pin assignments for the Artix-7 FPGA.
## ############################################################################################# ##
## PCIe
## ############################################################################################# ##
# PCIe Lanes
set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells
{PCIE_FW_UNIT_INST/B_XIL_PCIE_EP.I_PCIE_EP/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i
/gtp_channel.gtpe2_channel_i}]
set_property PACKAGE_PIN H2 [get_ports PER0_P]
set_property PACKAGE_PIN H1 [get_ports PER0_N]
set_property PACKAGE_PIN E4 [get_ports PET0_P]
set_property PACKAGE_PIN E3 [get_ports PET0_N]
# PCIe Reference Clock
set_property PACKAGE_PIN D6 [get_ports REFCLK_P]
set_property PACKAGE_PIN D5 [get_ports REFCLK_N]
# PERST
set_property IOSTANDARD LVCMOS33 [get_ports PERST_n]
set_property PACKAGE_PIN K1 [get_ports PERST_n]
## ############################################################################################# ##
## Front I/O
## ############################################################################################# ##
set_property IOSTANDARD LVCMOS33 [get_ports OE*]
set_property IOSTANDARD LVCMOS33 [get_ports DI*]
set_property IOSTANDARD LVCMOS33 [get_ports DO*]
set_property IOSTANDARD LVCMOS33 [get_ports PULL_*]
# Setting SLEW and DRIVE for Outputs only
set_property SLEW SLOW [get_ports OE*]
set_property DRIVE 4 [get_ports OE*]
set_property SLEW SLOW [get_ports DO*]
set_property DRIVE 4 [get_ports DO*]
set_property SLEW SLOW [get_ports PULL_*]
set_property DRIVE 4 [get_ports PULL_*]
set_property PACKAGE_PIN V9 [get_ports {OE[0]}]
set_property PACKAGE_PIN K17 [get_ports {OE[1]}]
set_property PACKAGE_PIN T12 [get_ports {OE[2]}]
set_property PACKAGE_PIN M16 [get_ports {OE[3]}]
set_property PACKAGE_PIN T18 [get_ports {OE[4]}]
set_property PACKAGE_PIN N16 [get_ports {OE[5]}]
set_property PACKAGE_PIN K15 [get_ports {OE[6]}]
set_property PACKAGE_PIN M15 [get_ports {OE[7]}]
set_property PACKAGE_PIN V11 [get_ports {OE[8]}]
set_property PACKAGE_PIN N14 [get_ports {OE[9]}]
set_property PACKAGE_PIN U16 [get_ports {OE[10]}]
set_property PACKAGE_PIN V17 [get_ports {OE[11]}]
set_property PACKAGE_PIN R15 [get_ports {OE[12]}]
set_property PACKAGE_PIN V16 [get_ports {OE[13]}]
set_property PACKAGE_PIN N18 [get_ports {DI[0]}]
set_property PACKAGE_PIN U10 [get_ports {DI[1]}]
set_property PACKAGE_PIN J14 [get_ports {DI[2]}]
set_property PACKAGE_PIN N17 [get_ports {DI[3]}]
set_property PACKAGE_PIN M17 [get_ports {DI[4]}]
set_property PACKAGE_PIN U17 [get_ports {DI[5]}]
set_property PACKAGE_PIN R17 [get_ports {DI[6]}]
set_property PACKAGE_PIN P18 [get_ports {DI[7]}]
set_property PACKAGE_PIN U12 [get_ports {DI[8]}]
set_property PACKAGE_PIN T17 [get_ports {DI[9]}]
set_property PACKAGE_PIN U11 [get_ports {DI[10]}]
set_property PACKAGE_PIN U14 [get_ports {DI[11]}]
set_property PACKAGE_PIN P15 [get_ports {DI[12]}]
set_property PACKAGE_PIN U9 [get_ports {DI[13]}]
