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Tews Technologies TMPE627 Скачать руководство пользователя страница 18

 

 

TMPE627 User Manual Issue 1.0.2 

Page 18 of 34 

  DAC Interface 

4.8

The DAC signals are accessible through the I/O bank 15 of the Artix-7 FPGA. 

Signal 

Bank 

V

CCO

 

Pin 

Description 

SCLK 

15 

3.3 V 

F17 

Serial Clock Input 

SDIN 

15 

3.3 V 

C11 

Serial Data Input 

SDO 

15 

3.3 V 

A15 

Serial Data Output 

SYNC# 

15 

3.3 V 

D10 

Frame synchronization signal 

LDAC# 

15 

3.3 V 

G14 

Load DAC 

CLR# 

15 

3.3 V 

F14 

Sets the DAC registers to zero-
scale or midscale code 

BIN2S 

15 

3.3 V 

B15 

DAC coding for a bipolar output 
range 

Table 4-16: DAC I/O Interface 

4.8.1  DAC 

All analog outputs are directly connected to DAC pins. 

Protection 

3.5 kV ESD HMB rating on analog input channels 

DC Output Impedance 

0.5 

Ω

 

Load 

2 k

Ω

 

Capacitive Load 

4000 pF 

Table 4-17: DAC Electrical Interface 

4.8.2  DAC Overcurrent Protection 

Generally the DAC’s “Automatic Channel Power-Down” overcurrent protection feature should be used 
instead of the current limit clamp. This minimizes the effect of a fault on a DAC output because of the limited 
power supply. 

In case of an overload condition, the DAC channel is powered down and its output is clamped to ground with 
a resistance of ~4 k

Ω. This condition is indicated by the OCx bit set to ‘1’ and the PUx set to ‘0’. The channel 

can be powered up again by setting the PUx bit back to ‘1’ after the overload condition is relieved. 

Содержание TMPE627

Страница 1: ...gurable FPGA with AD DA Digital I O PCIe Mini Card Version 1 0 User Manual Issue 1 0 2 January 2018 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 40...

Страница 2: ...duct described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions He...

Страница 3: ...27 User Manual Issue 1 0 2 Page 3 of 34 Issue Description Date 1 0 0 Initial Issue June 2017 1 0 1 Corrected typos October 2017 1 0 2 Changed Document Tilte Added A Remark About Slot Supplies January...

Страница 4: ...cking 11 4 4 4 4 1 FPGA Clock Sources 11 Digital I O Interface 12 4 5 4 5 1 TTL I O Interface 13 User GPIO 14 4 6 ADC Interface 15 4 7 4 7 1 ADC 16 DAC Interface 18 4 8 4 8 1 DAC 18 4 8 2 DAC Overcurr...

Страница 5: ...RVIEW 9 TABLE 4 2 FPGA BANK USAGE 9 TABLE 4 3 GTP CONNECTIONS 10 TABLE 4 4 GIGABIT TRANSCEIVER REFERENCE CLOCKS 10 TABLE 4 5 FPGA SPI FLASH CONNECTIONS 11 TABLE 4 6 AVAILABLE FPGA CLOCKS 11 TABLE 4 7...

Страница 6: ...24 V 5 V 5 12 V 10 V and 10 24 V with a sampling rate of up to 200 ksps Each TMPE627 is factory calibrated The calibration information is stored in an on board serial EEPROM unique to each TMPE627 mo...

Страница 7: ...ntial single ended ADC Analog Input Voltage Software selectable 0 5 12 V 0 10 V 0 10 24 V 5 V 5 12 V 10 V 10 24 V Analog Output Channels 4x 16 bit 10 s settling single ended DAC Analog Output Voltage...

Страница 8: ...3 2 The I O connector and the heatsink will exceed the available PCI Express Mini Card components height Check carefully if your application provides enough spacing for a TMPE627 Thermal Consideration...

Страница 9: ...0 2700 4 Table 4 1 TMPE627 FPGA Feature Overview The FPGA is equipped with 4 I O banks and 4 Gigabit GTP Transceivers One of the GTPs can be connected to an Endpoint Block for PCI Express Bank VCCO VR...

Страница 10: ...the TMPE627 GTP Signal FPGA Pins Connected to MGTREFCLK0 MGTREFCLK D5 D6 100 MHz backplane clock MGTREFCLK1 MGTREFCLK B5 B6 not connected Table 4 4 Gigabit Transceiver Reference Clocks User FPGA Confi...

Страница 11: ...ration feature the following configuration option must be set set_property BITSTREAM CONFIG EXTMASTERCCLK_EN div 1 current_design set_property CONFIG_VOLTAGE 3 3 current_design set_property CFGBVS VCC...

Страница 12: ...3 14 4 SLOW DI 11 U14 IN LVCMOS33 14 4 SLOW DI 12 P15 IN LVCMOS33 14 4 SLOW DI 13 U9 IN LVCMOS33 14 4 SLOW DO 0 V12 OUT LVCMOS33 14 4 SLOW DO 1 L18 OUT LVCMOS33 14 4 SLOW DO 2 T13 OUT LVCMOS33 14 4 SL...

Страница 13: ...put enable signal and provide a 47 serial resistor and a 4 7 k pull resistor The pull resistor guarantees a valid logic level when the outputs are tristate and not driven externally The pull voltage c...

Страница 14: ...1 1 Output Level Output Current Because of the 47 ohm series resistor there is a reduced high level voltage at the I O pin when the output buffer sources a noticeable current to the external load whi...

Страница 15: ...SDI 15 3 3 V G17 Data Input SDO0 15 3 3 V A17 Data Output 0 SDO1 SDI 15 3 3 V D13 Data Output 1 LVDS Data Input SDO2 SDI 15 3 3 V C13 Data Output 2 LVDS Data Input SDO3 SCKI 15 3 3 V E13 Data Output...

Страница 16: ...ry Format 10 24 V 20 48 V 5 12 V Two s Complement 10 V 20 V 5 V Two s Complement 5 12 V 10 24 V 2 56 V Two s Complement 5 V 10 V 2 5 V Two s Complement 0 V to 10 24 V 10 24 V 10 24 V Straight Binary 0...

Страница 17: ...round reference should be connected use the single ended input scheme or connect VIN and VIN to AGND with a resistor to prevent the signal source to float out of the ADC s common mode range In most ca...

Страница 18: ...directly connected to DAC pins Protection 3 5 kV ESD HMB rating on analog input channels DC Output Impedance 0 5 Load 2 k Capacitive Load 4000 pF Table 4 17 DAC Electrical Interface 4 8 2 DAC Overcur...

Страница 19: ...tails about the stored data The device address will be 1010000 SPI Flash Signal Bank VCCO Pin Description SCL 34 3 3 V R1 Serial Clock SDA 34 3 3 V T2 Serial Data Table 4 18 FPGA I C EEPROM Connection...

Страница 20: ...sink will violate the Mini PCIe Card component envelope Check carefully if your system provides enough spacing for a TMPE627 with mounted heatsink In space constrained systems mounting a heatsink may...

Страница 21: ...g factory calibration and are stored in an on board EEPROM as 2 complement 2 byte wide values in the range from 32768 to 32767 To achieve a higher accuracy they are scaled to LSB 4 12 1 Off Module Cor...

Страница 22: ...inCORR 5 V 16 0x014 ADC Channel 2 OffsetCORR 5 V 16 0x016 ADC Channel 2 GainCORR 5 V 16 0x018 ADC Channel 3 OffsetCORR 5 V 16 0x01A ADC Channel 3 GainCORR 5 V 16 0x01C ADC Channel 4 OffsetCORR 5 V 16...

Страница 23: ...nnel 1 GainCORR 10 24 V 16 0x064 ADC Channel 2 OffsetCORR 10 24 V 16 0x066 ADC Channel 2 GainCORR 10 24 V 16 0x068 ADC Channel 3 OffsetCORR 10 24 V 16 0x06A ADC Channel 3 GainCORR 10 24 V 16 0x06C ADC...

Страница 24: ...ffsetCORR 10 V 16 0x0BE DAC Channel 4 GainCORR 10 V 16 0x0C0 DAC Channel 1 OffsetCORR 10 8 V 16 0x0C2 DAC Channel 1 GainCORR 10 8 V 16 0x0C4 DAC Channel 2 OffsetCORR 10 8 V 16 0x0C6 DAC Channel 2 Gain...

Страница 25: ...scription Voltage Range Size Bit 0x1F8 Module Serial Number The Module Serial Number is stored as EUI 64 i e Sn 1234567 0x0001060001234567 It can be used to support the PCIe Device Serial Number Capab...

Страница 26: ...itstreams This allows the use of the Artix 7 MultiBoot feature Refer to Xilinx UG470 7 Series FPGAs Configuration User Guide for more details 6 Installation To install the PCI Express Mini Card insert...

Страница 27: ...Issue 1 0 2 Page 27 of 34 7 I O Connectors This chapter provides information about user accessible on board connectors Overview 7 1 X1 System Connector X2 I O Connector X3 JTAG Connector Figure 7 1 I...

Страница 28: ...46 LEP_WPAN GND 43 44 LEP_WLAN 3 3 Vaux 41 42 LEP_WWAN 3 3 Vaux 39 40 GND GND 37 38 USB_D GND 35 36 USB_D PETp0 33 34 GND PETn0 31 32 SMB_DATA GND 29 30 SMB_CLK GND 27 28 1 5 V PERp0 25 26 GND PERn0 2...

Страница 29: ...g for a TMPE627 Pin Assignment Description Pin Pin Description Single En Diff Single En Diff ADC 1 ADC 1 1 2 Connect to GND ADC 1 ADC 2 ADC 2 3 4 Connect to GND ADC 2 ADC 3 ADC 3 5 6 Connect to GND AD...

Страница 30: ...ides a Programming Kit TA308 which includes a XSR cable and an adapter module that provides a Xilinx USB Programmer II compatible 2 mm shrouded header Pin Description 1 GND 2 TCK 3 TMS 4 TDI 5 TDO 6 G...

Страница 31: ...erty SLEW SLOW get_ports PULL_ set_property DRIVE 4 get_ports PULL_ set_property PACKAGE_PIN V9 get_ports OE 0 set_property PACKAGE_PIN K17 get_ports OE 1 set_property PACKAGE_PIN T12 get_ports OE 2 s...

Страница 32: ...IVE 4 get_ports ADC_LVDS_CMOS_n set_property DRIVE 4 get_ports ADC_PD set_property DRIVE 4 get_ports ADC_SCKI_SCKI_N set_property DRIVE 4 get_ports ADC_SDI set_property PACKAGE_PIN C12 get_ports ADC_C...

Страница 33: ...5_SDA set_property PACKAGE_PIN H18 get_ports SE95_OS SPI Interface set_property IOSTANDARD LVCMOS33 get_ports SPI CCLK runs through STARTUPE2 set_property PACKAGE_PIN R16 get_ports CCLK set_property P...

Страница 34: ...RUE get_sites N1 PCIe Reference Clock create_clock period 10 000 get_ports REFCLK_P 100 MHz External Configuration Master Clock create_clock period 10 000 get_ports EMC_CLK General Config Settings set...

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