TMPE627 User Manual Issue 1.0.2
Page 11 of 34
SPI-Flash Signal
Bank
V
CCO
Pin
Description / Artix-7
CLK
0
3.3 V
E8
Serial Clock (CCLK)
CS#
14
3.3 V
L15
Chip Select (CS0_B)
DI (bit0)
14
3.3 V
K16
Serial Data input (MOSI) / MISO[0]
DO (bit1)
14
3.3 V
L17
Serial Data output (DIN) / MISO[1]
WP# (bit2)
14
3.3 V
J15
MISO[2]
HOLD# (bit3)
14
3.3 V
J16
MISO[3]
Table 4-5: FPGA SPI-Flash Connections
4.3.2 Configuration via JTAG
For direct FPGA configuration, FPGA read back or in-system diagnostics with ChipScope, the JTAG
connector can be used to access the FPGA JTAG port. Also an indirect SPI-Flash programming is possible
via the JTAG Chain.
4.3.3 Generate Artix-7 Configuration Data
To use the maximum configuration speed, the TMPE627 must be configured to use the 100 MHz external
master clock as CCLK.
To use this configuration feature, the following configuration option must be set:
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
To use the maximum data transfer speed of the User FPGA SPI Configuration Flash the SPI Configuration
Bus Width must be set to the x4.
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
Without this option, the configuration time for the Artix-7 FPGA exceed the maximum PCIe bus setup time.
Clocking
4.4
4.4.1 FPGA Clock Sources
The following table lists the available clock sources on the TMPE627:
FPGA Clock-Pin Name
FPGA Pin
Number
Source
Description
MGTREFCLK0_101
D5 / D6
PCI Express Mini Card
Slot
100 MHz
PCIe Reference clock
IO_L3N_T0_DQS_EMCCLK_14
K18
External oscillator
100 MHz
External master configuration
clock
Table 4-6: Available FPGA clocks
