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TR4 User Manual
5
www.terasic.com
March 30, 2017
Figure 1-3 TR4 Block Diagram
Below is more detailed information regarding the blocks in
Figure 1-3
.
Stratix IV GX FPGA
EP4SGX230C2
228,000 logic elements (LEs)
17,133 total memory Kb
1,288 18x18-bit multipliers blocks
2 PCI Express hard IP blocks
Содержание TR4
Страница 1: ...TR4 User Manual 1 www terasic com March 30 2017 y94 ...
Страница 45: ...TR4 User Manual 42 www terasic com March 30 2017 Figure 2 24 Clock Connections of the TR4 ...
Страница 58: ...TR4 User Manual 55 www terasic com March 30 2017 Figure 2 31 R199 R201 Position on TR4 ...
Страница 67: ...TR4 User Manual 64 www terasic com March 30 2017 Figure 3 7 Access DDR3 SO DIMM Memory ...
Страница 73: ...TR4 User Manual 70 www terasic com March 30 2017 Figure 3 13 Information Tab of TR4 Control Panel ...