Terasic TR4, Руководство пользователя

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TR4 User Manual 34 www.terasic.com
March 30, 2017
Figure 2-22 Connection between the GPIO Expansion Headers and Stratix IV GX
The information about mapping of the FPGA pin assignments to the GPIO0 and GPIO1 connectors,
please refer Table 2-13 and Table 2-14.
Table 2-13 GPIO Expansion Head e r (JP9) Pin Assignments, Schematic Signal Names, and
Functions
Board Reference
(JP9)
Schematic
Signal Name
Description I/O Standard
Stratix IV GX
Pin Number
1 GPIO0_D0 GPIO Expansion 0 IO[0](Clock In)
Depends on I/O
Standard of HSMC
Port C
PIN_AF34
2 GPIO0_D1 GPIO Expansion 0 IO[1] PIN_AG34
3 GPIO0_D2 GPIO Expansion 0 IO[2](Clock In) PIN_AE35
4 GPIO0_D3 GPIO Expansion 0 IO[3] PIN_AG35
5 GPIO0_D4 GPIO Expansion 0 IO[4] PIN_AC31
6 GPIO0_D5 GPIO Expansion 0 IO[5] PIN_AH32
7 GPIO0_D6 GPIO Expansion 0 IO[6] PIN_AC32
8 GPIO0_D7 GPIO Expansion 0 IO[7] PIN_AH33
9 GPIO0_D8 GPIO Expansion 0 IO[8] PIN_AH34
10 GPIO0_D9 GPIO Expansion 0 IO[9] PIN_AJ34
13 GPIO0_D10 GPIO Expansion 0 IO[10] PIN_AH35
14 GPIO0_D11 GPIO Expansion 0 IO[11] PIN_AJ35
15 GPIO0_D12 GPIO Expansion 0 IO[12] PIN_AK34
16 GPIO0_D13 GPIO Expansion 0 IO[13] PIN_AL34
17 GPIO0_D14 GPIO Expansion 0 IO[14] PIN_AK35
18 GPIO0_D15 GPIO Expansion 0 IO[15] PIN_AL35
19 GPIO0_D16 GPIO Expansion 0 IO[16] PIN_AM34
20 GPIO0_D17 GPIO Expansion 0 IO[17] PIN_AN34