Terasic HDMI-FMC, Руководство пользователя

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HDMI-FMC_User_Manual www.terasic.com
August 6, 2019
Table 3-7 Configuration of I2S Interface (RW)
Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x20
[95]
I
2
S Input Configuration Register
SCK Sample
Edge
0 – Falling
(change data
on rising
edge)
1 – Rising
MCLK Multiplier – the Tx uses these bits
to divide the MCLK input to produce CTS
values according to the 128•
f s formula.
The MCLK-to- f s ratio is for input f s, not
down-sampled output f s.
000 – 128 100 – 768
001 – 256 101 – 1024
010 – 384 110 – 1152
011 – 512 111 – 192
WS
Polarity
– Left
when:
0 – WS is
Low
1 – WS is
High
SD
Justify
Data is
justified:
0 – Left
1 –
Right
SD
Direction
Byte
shifted
first:
0 – MSB
1 – LSB
WS to
SD
First
Bit
Shift?
0 –
Yes
(per
spec)
1 – No
◼
Mapping of I2S Interface
Software typically writes TPI 0x1F multiple times, with a separate FIFO selected each time, to assign
SD pins to FIFOs. A single SD pin may be connected to multiple FIFOs. For example, the same SD0
pin could be assigned to FIFO#0, FIFO#1, FIFO#2, and FIFO#3 to provide eight audio output
channels. Unused FIFOs can be assigned to disabled SD inputs. No gaps are allowed when mapping
channels to FIFOs; SD pins must be mapped to FIFO#0 and FIFO#1 before mapping a channel to
FIFO#2, and so on.
Table 3-8 Mapping of I2S Interface (RW)
Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x1F
[00]
I
2
S Enable and Mapping Register
1
SD pin
selected by
[5:4]
0 – Disable
1 – Enable
RSVD
Select SD pin to be
connected
to a FIFO
00 – SD0
01 – SD1
10 – SD2
11 – SD3
Automatic
down-sample
to Basic
Audio mode
(FIFO#0
only)
0 – Disable
1 – Enable
Swap Left /
Right I
2
S
channels on
this channel
0 – No swap
1 – Swap
This FIFO will take its
input from the SD pin
selected in
bits [5:4]
00 – FIFO#0
01 – FIFO#1
10 – FIFO#2
11 – FIFO#3