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HDMI-FMC_User_Manual

www.terasic.com

August 6, 2019

RX_RD7

Output

Receiver video red data 7

1.5/1.8/2.5/3.0/3.3V

RX_RD8

Output

Receiver video red data 8

1.5/1.8/2.5/3.0/3.3V

RX_RD9

Output

Receiver video red data 9

1.5/1.8/2.5/3.0/3.3V

RX_RD10

Output

Receiver video red data 10

1.5/1.8/2.5/3.0/3.3V

RX_RD11

Output

Receiver video red data 11

1.5/1.8/2.5/3.0/3.3V

RX_RD12

Output

Receiver video red data 12

1.5/1.8/2.5/3.0/3.3V

RX_RD13

Output

Receiver video red data 13

1.5/1.8/2.5/3.0/3.3V

RX_RD14

Output

Receiver video red data 14

1.5/1.8/2.5/3.0/3.3V

RX_RD15

Output

Receiver video red data 15

1.5/1.8/2.5/3.0/3.3V

RX_MCLK

Output

Receiver audio master clock

1.5/1.8/2.5/3.0/3.3V

RX_SCLK

Output

Receiver audio serial clock

1.5/1.8/2.5/3.0/3.3V

RX_AP0

Output

Receiver audio data 0

1.5/1.8/2.5/3.0/3.3V

RX_AP1

Output

Receiver audio data 1

1.5/1.8/2.5/3.0/3.3V

RX_AP2

Output

Receiver audio data 2

1.5/1.8/2.5/3.0/3.3V

RX_AP3

Output

Receiver audio data 3

1.5/1.8/2.5/3.0/3.3V

RX_AP4

Output

Receiver audio data 4

1.5/1.8/2.5/3.0/3.3V

RX_AP5

Output

Receiver audio data 5

1.5/1.8/2.5/3.0/3.3V

ADV7619_CS_N

Input

Receiver chip select, active low

1.5/1.8/2.5/3.0/3.3V

ADV7619_INT

Output

Receiver interrupt signal

1.5/1.8/2.5/3.0/3.3V

ADV7619_RESET_N

Input

Receiver reset signal, active low

1.5/1.8/2.5/3.0/3.3V

ADV7619_CSCL_F

Input

Receiver I2C serial clock

1.5/1.8/2.5/3.0/3.3V

ADV7619_CSDA_F

Input/Output

Receiver I2C serial data

1.5/1.8/2.5/3.0/3.3V

RX0_DDC_SCL

Input

Receiver EDID controller serial clock port A

1.5/1.8/2.5/3.0/3.3V

RX0_DDC_SDA

Input/Output

Receiver EDID controller serial data port A

1.5/1.8/2.5/3.0/3.3V

RX1_DDC_SCL

Input

Receiver EDID controller serial clock port B

1.5/1.8/2.5/3.0/3.3V

RX1_DDC_SDA

Input/Output

Receiver EDID controller serial data port B

1.5/1.8/2.5/3.0/3.3V

Note : 1. For I/O standard, 3.0 V is applied to High-end FPGAs and 3.3 V is applied to Low Cost and

Power FPGAs.

2. The RX pixel color-bit plane is adjustable accord to the video interface data format

settings,including video format and data width.

Содержание HDMI-FMC

Страница 1: ......

Страница 2: ...3 1 3 Getting Help 3 Chapter 2 Introduction of the HDMI FMC Card 4 2 1 Features 5 2 2 Block Diagram of the HDMI FMC Board 7 2 3 Connectivity 8 Chapter 3 Using the HDMI FMC Board 10 3 1 Sil9136 3 10 3 2 ADV7619 26 3 3 Level shift 27 3 4 FMC Connector 29 Chapter 4 Example Codes 34 4 1 4K HDMI Loopback Demonstration 34 Chapter 5 Appendix 45 ...

Страница 3: ...ormat most common 3D formats and the video resolution up to 8 bit 4K 30Hz 12 bit 1080p 60Hz 12 bit 720p 1080i 120 Hz and 16 bit 1080p 30 Hz The audio interface supports S PDIF DSD I2S and HBR audio format input The Rx module is able to support all mandatory and additional 3D video formats and extended colorimetry sYCC601 Adobe RGB Adobe YCC601 xvYCC extended gamut color CEC 1 4 compatible with up ...

Страница 4: ...ains all the documents and supporting materials associated with HDMI FMC including the user manual reference designs and device datasheets Users can download this system CD from the link http hdmi fmc terasic com cd 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Ema...

Страница 5: ...iguration of the HDMI FMC Board including block diagram and components related Figure 2 1 The HDMI FMC Board PCB and Component Diagram of top side The Photographs of the HDMI FMC are shown in Figure 2 1 and Figure 2 2 They depict the layout of the board and indicates the location of the connectors and the key components on the top and bottom side ...

Страница 6: ...Board HDMI TX chip SiI9136 3 HDMI TX chip ADV7619 LEVEL Shift EPM2210 FMC Connector HPC 2 1 Features The HDMI FMC card has many features that allow users to implement a wide range of design circuits from simple circuits to various multimedia projects The following hardware is provided on the board Package Interface VITA 57 1 FMC adjustable I O standard 1 5 1 8 2 5 3 0V Tx Module ...

Страница 7: ...asic com August 6 2019 Chip P N SiI9136 3 HDMI 1 4a 1 3 HDCP 1 4 and DVI Compliant Video formats 4 4 4 RGB 4 4 4 4 2 2 YCbCr Pixels resolution 4Kx2K 30Hz Pixels clock DDR SDR up to 300MHz 3D format support High Bitrate Audio support ...

Страница 8: ...FMC Block Diagram Level shift module outputs audio and video image data from FMC connector which can be converted to TMDS data by passing through the Sil9136 3 to the HDMI TX connector Similarly HDMI RX connector receives all mandatory 3D TV formats defined in the HDMI 1 4a specification through a dual input HDMI capable which can be converted to audio and video image data by the ADV7619 and send ...

Страница 9: ...ic HDMI FMC is able to connect on to any FPGA development kit equiped with FMC High Pin Count connector The Below pictures Figure 2 4 Figure 2 5 and Figure 2 6 show the connections with three different Terasic FPGA Boards Figure 2 4 Connect the HDMI FMC to TR5 board s FMCD port ...

Страница 10: ... 9 HDMI FMC_User_Manual www terasic com August 6 2019 Figure 2 5 Connect the HDMI FMC to A10SoC board s FMCA port Figure 2 6 Connect the HDMI FMC to Terasic HAN Pilot Platform FMC port ...

Страница 11: ...0 Hz 12 bit 1080i 120 Hz and 16 bit 1080p 30Hz For audio input it supports I2S Direct Stream Digital and S PDIF audio input formats For HDMI output DVI and HDMI transmitter with xvYCC extended color gamut Deep Color up to 16 bit color and high bitrate audio are all supported The I2C address for TPI CR of Sil9136 3 is 0x72 0x7A Figure 3 1 shows the system block diagram of Sil9136 3 Figure 3 1 Sil91...

Страница 12: ...o capture block supports I2S Direct Stream Digital and S PDIF audio input formats The appropriate registers must be configured to describe the audio format provided to the SiI9136 3 transmitter There is a Transition minimized differential signaling TMDS transmitter for the output The TMDS digital core performs 8 to 10 bit TMDS encoding and is then sent over three TMDS data and a TMDS clock differe...

Страница 13: ...0x72 0xC7 to enable TPI mode 2 Detect Revision 0x1B 0x1D host TPI Detect Tx type and TPI revision When TPI 0x1B can be read correctly the TPI subsystem is ready 3 Power up transmitter 0x1E host TPI Enable active mode Write TPI 0x1E 1 0 00 4 Configure Input Bus and Pixel Repetition 0x08 host TPI Select input bus characteristics like pixel size clock edge 5 Select YC Input Mode 0x0B host TPI Select ...

Страница 14: ...egister 82 c Read 0xBE Read current value d Modify bit 0 1 Enable source termination e Write 0xBE Write back modified value SiI9136 3 Tx only This device requires the TMDS PLL bandwidth control to be set for 0 75x operation After powering up the transmitter the host should write the following sequence to set the bandwidth control for 0 75x operation a Write 0xBC 0x01 Internal page 0 b Write 0xBD 0...

Страница 15: ...nput and Output Format Defines color space color depth 0x0C 0x19 AVI InfoFrame Programs header information as defined by HDMI specification 0xBF 0xDE Other InfoFrame 0x60 YC Mux Mode System Control single byte control for most used functions 0x1A System Control Requests DDC bus access selects between DVI HDMI controls TMDS output and AV Mute Interrupt single byte status for monitoring significant ...

Страница 16: ...12 TPI Input Bus and Pixel Repetition Data Input Video Mode Data The input bus clocking format along with clocking rate and edge are specified in this register The video host also indicates the pixel repetition factor here Access This register is accessed as a single byte Table 3 4 TPI Input Bus and Pixel Repetition Data R W Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x08 60 InputBusFm...

Страница 17: ...first and when it is 1 data present at the rising edge is latched first The high order bits are latched first TClkSel If the video host drives in data using anything other than a 1 1 ratio of input clock speed to TMDS clock speed the host must program the clock multiplier logic TPI AVI Input and Output Format Input Format and Output Format are used by the host to specify the data format and range ...

Страница 18: ...now Access These registers can be accessed individually or by bursts as desired For writes the actual write to the HDMI transmitter logic takes place only once the final byte of the burst write to TPI 0x0C 19 occurs refer to Input Color Space Output Format note above Table 3 5 TPI AVI Input and Output Format Data R W Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x09 InputFormat 00 Input ...

Страница 19: ...r any non Deep Color mode of operation Unlike the other bits in this register any output color depth setting change takes place immediately and is not dependent on a write to the AVI InfoFrame registers Note Selecting any Deep Color output mode is done directly through TPI 0x0A 7 6 However if it is later necessary to switch back to 8 bit color depth switch to 16 bit Deep Color first and then to 8 ...

Страница 20: ...s can be enabled together by enabling the features of each group with TPI 0x60 7 set appropriately Access These registers are accessed as single bytes or as part of a burst Table 3 6 Sync Register Configuration and Sync Monitoring Registers Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x60 04 Sync Generation Control Register Sync Method 0 External 1 Embedded RSVD YC Mux Mode One to two d...

Страница 21: ...e F bit With explicit syncs the transmitter encodes HSYNC and VSYNC across the HDMI TMDS link without regard for field sequence I2S Input Configuration Register Configuring Audio Using I2S The I2S audio subsystem selection is made by TPI control I2S Initialization and Operation The transmitter requires the following initialization for I2S applications 1 Ensure that a valid I2S audio stream is comi...

Страница 22: ... 0x1F multiple times with a separate FIFO selected each time to assign SD pins to FIFOs A single SD pin may be connected to multiple FIFOs For example the same SD0 pin could be assigned to FIFO 0 FIFO 1 FIFO 2 and FIFO 3 to provide eight audio output channels Unused FIFOs can be assigned to disabled SD inputs No gaps are allowed when mapping channels to FIFOs SD pins must be mapped to FIFO 0 and F...

Страница 23: ...S Channel Status Byte 1 Category Code cbit15 cbit14 cbit13 cbit12 cbit11 cbit10 cbit9 cbit8 0x23 00 I2 S Channel Status Byte 2 Source Channel Number I2S Channel Number cbit23 20 I2S Source Number cbit19 16 0x24 0F I2S Channel Status Byte 3 Accuracy Sampling fs Clock Accuracy cbit31 28 Sampling Frequency cbit27 24 0000 44 1kHz 1000 88 2kHz 1100 176 4kHz 0010 48kHz 1010 96kHz 1110 192kHz 0011 32kHz ...

Страница 24: ... Status Change 0 Disable 1 Enable Audio Error Event 0 Disable 1 Enable CPI Event in place of Rx Sense 0 Disable 1 Enable RSVD Receiver Sense Event 0 Disable 1 Enable Hot Plug Connection cable plugged unplugged Event 0 Disable 1 Enable Interrupt Status Register The Interrupt Status Register shows current status of interrupt events even if the event has been disabled This register can be polled for ...

Страница 25: ...ction The Hot Plug state HTPLG signal from the DVI or HDMI sink indicates whether a display is attached the EDID is readable but the display is not necessarily powered up The Hot Plug event indicates whether the state has changed Receiver Sense The Receiver Sense state RxSense signal from HDCP indicates whether a powered up receiver is sensed whether the TMDS lines are being pulled externally to 3...

Страница 26: ...S input are reported Security Status Change Any change in the link status value TPI 0x29 5 4 generates a Security Status Change event so the host can take appropriate action to re establish the link HDCP V Value Ready Once a V value is selected this event indicates that the computation has completed and the value is available TPI 0x31 3 1 HDCP Authentication Status Change An authentication status ...

Страница 27: ...tus bit for TMDS Clock Stable there is a TPI Interrupt TPI 0x3E 0 for TMDS Clock Stable and a corresponding Interrupt Enable TPI 0x3F 0 Alternative TMDS Clock Stable Similar to TMDS Clock Stable but uses alternative method for clock checking There is no interrupt associated with this bit change 3 2 ADV7619 A DV7619 is a high quality with two input ports and one output multiplexed High Definition M...

Страница 28: ..._v 1 1 0_SystemCD zip Datasheet for the register tables of HDMI Receiver chip ADV7619 3 3 Level shift For the voltage matching between FMC connector and HDMI transmitter receiver IC EPM2210 LSF0102 and TXB0104 are employed for the level shift For HDMI transmitter receiver IC the I O voltage is 3 3V while the I O voltage of all four FMC connectors is adjustable within 1 2 1 5 1 8 2 5 3 0V The MAX I...

Страница 29: ...rt and 1 65 to 5 5 V on B port LSF0102 and TXB0104 are employed for the voltage translation of I2C and audio data Figure 3 3 Figure 3 4 Figure 3 5 gives an illustration of the level shift Figure 3 3 Voltage translation of I2C for Receiver Figure 3 4 Voltage translation of audio data for receiver ...

Страница 30: ...tion signal 1 5 1 8 2 5 3 0 3 3V TX_DE Input Transmitter data enable 1 5 1 8 2 5 3 0 3 3V TX_BD0 Input Transmitter video blue data 0 1 5 1 8 2 5 3 0 3 3V TX_BD1 Input Transmitter video blue data 1 1 5 1 8 2 5 3 0 3 3V TX_BD2 Input Transmitter video blue data 2 1 5 1 8 2 5 3 0 3 3V TX_BD3 Input Transmitter video blue data 3 1 5 1 8 2 5 3 0 3 3V TX_BD4 Input Transmitter video blue data 4 1 5 1 8 2 5...

Страница 31: ... 5 3 0 3 3V TX_GD10 Input Transmitter video green data 10 1 5 1 8 2 5 3 0 3 3V TX_GD11 Input Transmitter video green data 11 1 5 1 8 2 5 3 0 3 3V TX_RD0 Input Transmitter video red data 0 1 5 1 8 2 5 3 0 3 3V TX_RD1 Input Transmitter video red data 1 1 5 1 8 2 5 3 0 3 3V TX_RD2 Input Transmitter video red data 2 1 5 1 8 2 5 3 0 3 3V TX_RD3 Input Transmitter video red data 3 1 5 1 8 2 5 3 0 3 3V TX...

Страница 32: ...asynchronous reset signal active low 1 5 1 8 2 5 3 0 3 3V SIL9136_INT Output Transmitter interrupt signal 1 5 1 8 2 5 3 0 3 3V SIL9136_CSCL_FM C Input Transmitter configuration status I2C serial clock 1 5 1 8 2 5 3 0 3 3V SIL9136_CSDA_FM C Input Output Transmitter configuration status I2C serial data 1 5 1 8 2 5 3 0 3 3V RX_PCLK Output Receiver pixel data clock 1 5 1 8 2 5 3 0 3 3V RX_HS Output Re...

Страница 33: ... 3V RX_GD4 Output Receiver video green data 4 1 5 1 8 2 5 3 0 3 3V RX_GD5 Output Receiver video green data 5 1 5 1 8 2 5 3 0 3 3V RX_GD6 Output Receiver video green data 6 1 5 1 8 2 5 3 0 3 3V RX_GD7 Output Receiver video green data 7 1 5 1 8 2 5 3 0 3 3V RX_GD8 Output Receiver video green data 8 1 5 1 8 2 5 3 0 3 3V RX_GD9 Output Receiver video green data 9 1 5 1 8 2 5 3 0 3 3V RX_GD10 Output Rec...

Страница 34: ...AP3 Output Receiver audio data 3 1 5 1 8 2 5 3 0 3 3V RX_AP4 Output Receiver audio data 4 1 5 1 8 2 5 3 0 3 3V RX_AP5 Output Receiver audio data 5 1 5 1 8 2 5 3 0 3 3V ADV7619_CS_N Input Receiver chip select active low 1 5 1 8 2 5 3 0 3 3V ADV7619_INT Output Receiver interrupt signal 1 5 1 8 2 5 3 0 3 3V ADV7619_RESET_N Input Receiver reset signal active low 1 5 1 8 2 5 3 0 3 3V ADV7619_CSCL_F MC ...

Страница 35: ...configured as 2 24 bit SDR 4 4 4 interleaved Mode 0 In this case the ADV7619 will output two pixels per video clock A DDIO IP is used to convert two pixels to one pixel by twice the video clock The HDMI TX Chip SiI9136 3 is configured as RGB input and RGB output mode A Nios II Processor is used to configure the HDMI TX and RX chips through the I2C interfaced There are two HDMI RX ports on the boar...

Страница 36: ...l www terasic com August 6 2019 Figure 4 1 System block diagram of the HDMI loopback demonstration HAN Loopback Demonstration Setup Figure 4 2 shows the hardware setup of loopback demonstration for Terasic HAN Pilot Platform ...

Страница 37: ...2 Set FMC VADJ as 1 8V by shorting pin 5 pin 6 of JP2 on the HAN Pilot Platform 3 Connect the FMC HDMI daughter board to HAN board via FMC connector and make sure the screws on the HDMI FMC card have been tightened firmly 4 Connect the 4K HDMI monitor and the HDMI TX port with a HDMI cable power on the monitor and make sure the monitor is set to HDMI input mode 5 Connect the 4K HDMI source device ...

Страница 38: ...k Demonstration Setup Figure 4 3 shows the hardware setup of loopback demonstration for Terasic TR5 FPGA Mainboard Figure 4 3 Hardware setup of HDMI loopback demonstration for TR5 System Requirements The following items are required for TR5 Loopback demonstration HDMI FMC board x1 TR5 board x1 4K HDMI monitor 4K HDMI Source Device x1 HDMI Cable x2 Operation Please follow the steps below to set up ...

Страница 39: ...is set to HDMI input mode 5 Connect the 4K HDMI source device such as HDMI video player and HDMI RX port HDMI RX0 or HDMI RX1 port on the FMC HDMI board with a HDMI cable power on the HDMI source device and make sure its HDMI port is selected as the output 6 Connect PC with TR5 board TR5 USB Blaster II port via a mini USB cable 7 Power on TR5 board 8 Execute the batch file test bat under the folde...

Страница 40: ...tion of modifying the resistors is unskilled or improper it may have the risk of damaging the board hardware So please be careful when modifying the resistors Remove the resistors on the R612 and R613 positions in the red box then install 0 Ohm resistors on the R610 and R611 positions in the green box as shown in Figure 4 5 In the default resistors setting the TX_PCLK and SiI9136_RST_N signals are...

Страница 41: ...s shown in Figure 4 6 In the default resistors setting the RX_RD14 and RX_RD15 signals don t input to FPGA the red color will be not normal After modifying this group of resistors the red color will display normally Figure 4 5 The resistors need to be reworked Figure 4 6 The resistors need to be reworked Figure 4 7 shows the resistors that need to be reworked positions on A10SoC Production board P...

Страница 42: ...2019 Figure 4 7 The resistors positions on the PCB 2 Make sure Quartus 18 1 or later version has been installed on your PC 3 Program the max5 pof code into A10SoC I O MAX V as the steps below Set the switches of the SW3 as shown in the Figure 4 8 first ...

Страница 43: ...PC with A10SoC USB Blaster II connector via USB cable Then power on the A10SoC board open the Quartus Programmer tool click Auto Detect see Figure 4 9 Figure 4 9 Quartus Programmer windows Select the max5 pof file in the A10SoC_HDMI_FMC demo_batch folder into the MAX V device see Figure 4 10 ...

Страница 44: ...st 6 2019 Figure 4 10 Select the max5 pof file Click Start button to program as shown in Figure 4 11 Figure 4 11 Program the max5 pof After programming successfully power off the A10SoC board and set the switches of the SW3 as shown in Figure 4 12 ...

Страница 45: ...MI cable power on the monitor and make sure the monitor is set to HDMI input mode 6 Connect the 4K HDMI source device such as HDMI video player and HDMI RX port HDMI RX0 or HDMI RX1 port on the FMC HDMI board with a HDMI cable power on the HDMI source device and make sure its HDMI port is selected as the output 7 Connect PC with A10SoC board USB Blaster II port via a mini USB cable 8 Power on A10S...

Страница 46: ...ure 2 3 and Figure 3 1 V1 3 2018 3 7 Add Register Tables and Demo Setup Steps V1 4 2018 7 3 Modify steps number from 10 11 12 to 8 9 10 in Page 43 44 and marked as red color V1 5 2019 6 28 Modify section 4 1 add new operation step 2 for TR5 demo V1 6 2019 08 05 Add HAN HDMI FMC demo change the A10SoC ES board to A10SoC Production board 5 2 Copyright Statement Copyright 2017 Terasic Inc All rights ...

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