Terasic HDMI-FMC, Руководство пользователя

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HDMI-FMC_User_Manual www.terasic.com
August 6, 2019
implemented.
Input Configuration –
one-time
configuration of the
input bus for its
application
environment.
0x08 Input Bus and Pixel Repetition
Selects input bus characteristics such as
pixel size and clock edge
0x0B YC Input Mode Select Selects YC Mux modes, signal timing
features, and chooses sync method registers
to access
0x60–61 Sync Configuration and Monitoring
0x62–6D with
0x60[7] = 0
Explicit Sync DE Generation
Defines parameters for explicit sync
method
0x62–6D with
0x60[7] = 1
Embedded Sync Extraction
Defines parameters for embedded sync
method
Audio Configuration 0x1F–0x28 Audio Configuration Configures audio input channels and rates
Video Mode Select-
resolution, color
space,
InfoFrame headers
0x00–0x07 Video Mode Defines the incoming resolution
0x09–0x0A Input and Output Format Defines color space, color depth
0x0C–0x19 AVI InfoFrame
Programs header information as defined by
HDMI specification 0xBF– 0xDE Other InfoFrame
0x60 YC Mux Mode
—
System
Control-single-byte
control for most-used
functions
0x1A System Control
Requests DDC bus access, selects between
DVI/HDMI, controls TMDS output and
AV Mute
Interrupt – single-byte
status for monitoring
significant events
0x3C–0x3D Interrupt
Polls for and clears events, selects the
interrupt events that should cause hardware
INT activation
Power Control 0x1E Power Control
Selects full-power operational mode or
low-power standby mode
HDCP – automatic
security
0x29–0x3A HDCP Sets up and monitors HDCP link security
◼
TPI Identification Registers & Device ID Information
The ID registers return the device ID and TPI revision ID. The ID registers are listed in Table 3-2 .
HDCP-capable and non HDCP-capable transmitters are distinguishable only by reading the HDCP
revision register (TPI 0x30).
Access . These registers are accessed as single bytes.