Teledyne Lecroy PCI Express 2.0 Mid-Bus Probe, Инструкция по установке и эксплуатации, Страница: 13 / 29

Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1
13
4 Electrical Design
4.1 Probe Loading Effect
The logical probing of the PCI Express bus is achieved by tapping a small amount of energy from the probed signals and
channeling this energy to the analyzer. In order to avoid excessive loading conditions, the Teledyne LeCroy mid-bus
probe employs high impedance tip resistors (isolation resistors). The probe isolation resistance is selected to both satisfy
the probe sensitivity and system parasitic load requirements.
Extensive care has been taken to reduce the parasitic effect of the probed signals during each phase of the mid-bus
probe design. An equivalent Spice model is available via the Teledyne LeCroy Protocol Systems Group support team
(psgsupport@teledynelecroy.com)
With this unique design, the Teledyne LeCroy mid-bus probes can capture bus traffic signals with amplitudes specified by
the PCI Express standard, while introducing only the loss and added jitter that are within the recommended specification
in the PCI Express Mid-Bus Probing Footprint and Pinout.
4.2 Overview of Probe - Pin Assignments
Cross-references from the PCI Express Mid-Bus Probing Footprint and Pinout (8/05/03) Revision 1.0 are given in tables
listed below.
In the pinout tables that follow, the following variations may be applied:

The designation of upstream and downstream may be reversed as long as it is reversed for every lane (all
upstream connections on the left and all downstream on the right may be swapped)

Lane ordering may be reversed if done as a whole such that probe lanes 0, 1, 2, 3 connect to physical lanes 3, 2,
1, 0.

Each differential signal pair may have the D+ and D- assignment reversed.

If the Gen2 footprint is used, an additional ground pin is present above Pin1 and below Pin 24.