1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
Title
Number
Revision
Size
B
Date:
12/3/2010
Sheet of
File:
N:\PCBMGR\..\05466p1_b.schdoc
Drawn By:
REV
CHANGE
ENG
1 12/19/05
CAC
VCC
RE1/WR/AD9
3
RE0/RD/AD8
4
RG0/CCP3
5
RG1/TX2/CK2
6
RG2/RX2/DT2
7
RG3/CCP4
8
MCLR/VPP
9
RG4/CPP5
10
VS
S
11
VD
D
12
RD7/PSP7/AD7
63
RD6/PSP6/AD6
64
RD5/PSP5/AD5
65
RD4/PSP4/AD4
66
RD3/PSP3/AD3
67
RD2/PSP2/AD2
68
RD1/PSP1/AD1
69
RD0/PSP0/AD0
72
AV
DD
25
AV
S
S
26
RA3/AN3/VREF+
27
RA2/AN2/VREF-
28
RA1/AN1
29
RA0/AN0
30
VS
S
31
VD
D
32
RA5/AN4/LVDIN
33
RA4/T0CKI
34
RC1/T1OSI/CCP2
35
RC0/T1OSO/T13CLK
36
RC6/TX1/CK1
37
RC7/RX1/DT1
38
RC2/CCP1
43
RC3/SCK/SCL
44
RC4/SDI/SDA
45
RC5/SDO
46
RB7/KBI3/PGD
47
VD
D
48
OSC1/CLKI
49
OSC2/CLKO/RA6
50
VS
S
51
RB6/KBI2/PGC
52
RB5/KB11/PGM
53
RB4/KBI0
54
RB3/INT3/CCP2
55
RB2/INT2
56
RB1/INT1
57
RB0/INT0
58
RF7/SS
13
RF6/AN11
14
RF5/AN10/CVREF
15
RF4/AN9
16
RF3/AN8
17
RF2/AN7/C1OUT
18
RF1/AN6/C2OUT
23
VS
S
70
VD
D
71
RF0/AN5
24
RE7/CCP2/AD15
73
RE6/AD14
74
RE5/AD13
75
RE4/AD12
76
RE3/AD11
77
RE2/CS/AD10
78
RH6/AN14
20
RH5/AN13
21
RH4/AN12
22
RH3/A19
2
RH2/A18
1
RH1/A17
80
RH0/A16
79
RH7/AN15
19
RJ3/WRH
59
RJ2/WRL
60
RJ1/OE
61
RJ0/ALE
62
RJ4/BA0
39
RJ5/CE
40
RJ6/LB
41
RJ7/UB
42
U4
PIC18F8720
IC__286
VCC
VCC
1
2
3
4
5
6
J2
520425-3
VCC
ICD/PGM CONN
VCC
R16
10.2k
1
2
3
4
S1
MC
L
R
C3
N/I
1
2
3
4
J4
HEADER 4 PIN
R4
10.2k
DEFAULTS
VCC
2
OUT
3
4
OE
1
X1
MI100HH-25
EL0000022
C25
0.1 uF, 50V
C15
1 uF, 10V
C17
1uF, 10V
OSC in ECIO Mode
Initial Release
lampEnable
CPU ALIVE
DS4
GRN
1K
R8
1
TP9
SET_DEFAULTS
R3
10.2k
R27
10.2k
JP1
JP2
I2C Address Jumpers
Hardware Version Index
Teledyne - API
M100EU Sync/Demod PCA
05466
B
1
5
RT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J5
MICROFIT-16
preamp connector (inside housing)
SDA3
SCL3
HVPSGND
1k
R44
VCC
DIGITAL LAMP ENABLE AND I2C SIGNALS TO LAMP DRIVER
HVPS_MON
SCL2
SDA2
osc_out
I2C STATUS1
DS3
GRN
1K
R7
I2C_STATUS2
DS2
GRN
1K
R6
ALIVE
I2C_STATUS1
I2C_STATUS2
ALIVE
I2C_STATUS1
I2C_STATUS2
I2C STATUS3
DS1
GRN
1K
R5
I2C_STATUS3
I2C_STATUS3
VCC
SDA3
SCL3
R57
2k
R41
2k
VCC
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
I2C_SCL
I2C_SDA
I2C_SDA
I2C_SCL
SDA2
SCL2
OTEST
ETEST
POT_CS
MUX_A0
MUX_A1
MUX_A2
AD1_CS
SPI_SCK
SPI_SDI
SPI_SDO
PMT
PMTGND
OT_LED_DRIVE
OT_LED_RETURN
THE
MCLR
This schematic refers to 05464 PCB Rev B, 05465 PCA
REV 2 4/2/06
CAC
Fixed planes on solder and comp layers
SPI_SDI2
SPI_SDO2
SPI_SCK2
i Net Class
i Net Class
i Net Class
TP14
TP6
TP17
TP20
TP11
TP15
TP10
TP21
TP26
*
TP18
*
TP19
*
-12V
+12V
REV A 2/12/07
RJ
E-test, PMT Gain, Anti-Alias Fliter, Misc Cleanup
1
3
2
D8
BAS70-04
1
3
2
D9
BAS70-04
1
3
2
D12
BAS70-04
1
3
2
D11
BAS70-04
VCC
VCC
1k
R29
1k
R24
1k
R2
1k
R17
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
i Net Class
R63
1k
PGN
HVPWR
HVGND
+
10uF,35V
C101
C102
1uF, 10V
C104
1uF, 10V
+
10uF,35V
C106
+
10uF,35V
C105
+
10uF,35V
C103
VCC
PRINTED DOCUMENTS ARE UNCONTROLLED
DCN5897
9480 Carroll Park Drive, San Diego, CA 92121-5201
REV B 12/03/10 Added C46,47,48 & R65,66, fixed U11 power pins.
RT
D-10
06840B DCN6201
Содержание T100U
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