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Contents
ii
TDS 510A Performance Verification and Specifications
List of Figures
Figure 1–1: Map of Display Functions
1–3
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Figure 1–2: Verifying Adjustments and Signal-Path Compensation
1–6
.
Figure 1–3: Universal Test Hookup for Functional Tests
1–8
. . . . . . . . . .
Figure 1–4: Measurement of DC Offset Accuracy at Zero Setting
1–25
. . .
Figure 1–5: Initial Test Hookup
1–26
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Figure 1–6: Measurement of DC Accuracy at Maximum Offset
and Position
1–28
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Figure 1–7: Initial Test Hookup
1–30
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Figure 1–8: Measurement of Analog Bandwidth
1–32
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Figure 1–9: Initial Test Hookup
1–34
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Figure 1–10: Measurement of Channel Delay
1–36
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Figure 1–11: Initial Test Hookup
1–38
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Figure 1–12: Measurement of Accuracy — Long-Term and
Delay Time
1–40
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Figure 1–13: Initial Test Hookup
1–41
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Figure 1–14: Measurement of Time Accuracy for Pulse and
Glitch Triggering
1–43
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Figure 1–15: Initial Test Hookup
1–44
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Figure 1–16: Measurement of Trigger-Level Accuracy
1–46
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Figure 1–17: Initial Test Hookup
1–48
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Figure 1–18: Measurement of Trigger Sensitivity — 50 MHz Results
1–51
Figure 1–19: Initial Test Hookup
1–53
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Figure 1–20: Measurement of Main Trigger Out Limits
1–55
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Figure 1–21: Initial Test Hookup
1–57
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Figure 1–22: Measurement of Probe Compensator Frequency
1–58
. . . . .
Figure 1–23: Subsequent Test Hookup
1–59
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Figure 1–24: Measurement of Probe Compensator Amplitude
1–60
. . . . .
Figure 1–25: Jitter Test Hookup
1–62
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Figure 1–26: Jitter Test Displayed Waveform
1–63
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Figure 1–27: Jitter Test When Completed
1–64
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Figure 1–28: Triggered Signal Range Test – 300 mV
1–66
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Figure 1–29: Triggered Signal Range Test – 75 mV
1–67
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Figure 1–30: 60 Hz Rejection Test Hookup
1–68
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Figure 1–31: 60 Hz Rejection Test Setup Signal
1–68
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Figure 1–32: Subsequent 60 Hz Rejection Test Hookup
1–69
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Figure 1–33: 60 Hz Rejection Test Result
1–70
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Содержание TDS 510A
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