Specifications
1-10
RTX100A ISDB-T RF Signal Generator Service Manual
188 bytes
DATA 0--7
DCLK
PSYNC
DVALID
DATA 0--7
DCLK*
DATA 0--7
DCLK*
Output data delay
Input clock pulse width
Input data hold time
Th
T/2
T/10
T (f/1)
5 ns
5 ns
* In the universal parallel/serial interface,
the polarity of DCLK can be inverted.
Th = T/2
T/10: SPI and universal parallel interfaces
Th = T/5
T/10: universal serial interface
Transition period
Figure 1-1: Timing diagram of the SPI and universal parallel/serial interfaces
Содержание RTX100A
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