Tektronix RTX100A, Руководство по обслуживанию

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Theory of Operation
2-2
RTX100A ISDB-T RF Signal Generator Service Manual
PCR/DTS Updater.
This block consists of a PCR counter and update logic. The
PCR counter is a complex counter, which consists of a 300-notation counter and
33-bit counter. The counter counts the 27 MHz standard frequency. The update
logic replaces the PCR and PTS/DTS values in a transport stream with the sum
of the original value and the PCR counter value.
Receive Rate Counter.
This 24-bit counter is used for receive-rate calculation on
recording process. When used a data valid signal (DVALID), the counter counts
byte data rate. When not used DVALID, the counter counts receive clock.
Transmit Byte Counter.
This 32-bit counter counts transmitted bytes. This counter
can be read by the control software.
Receive Rate Counter.
This circuit detects receive rate. Its status is updated every
50 ms.
The interrupt controller sends the following interruption signals to the CPU: Play
FIFO empty, Record FIFO full, external trigger, 10 Hz, Playout DMA transfer
finished, and Record DMA transfer finished. These interruptions can be disabled
by the RTX100A application software. At power on, all interruptions are
disabled.
The TS clock generator consists of a VCO (Voltage Control Oscillator), phase
detector, frequency divider. The VCO is used for generating a TS clock, and it
covers frequencies of 400 MHz to 800 MHz. The frequency divider divides the
clock by 65536 to 1.
The reference clocks consist of 27 MHz TCXO and half-divided output of
54 MHz clock generator. These clocks are used to compare the frequency of the
TS Clock Generator.
Interrupt Controller
TS Clock Generator
Reference Clocks