Theory of Operation
MTX100A MPEG Recorder & Player Service Manual
2-7
When the data rate from the MTX100A storage (hard disk or RAM) is lower
than 216Mbps, it is possible to select whether to sparsely output all the data or to
output the data on a packet-by-packet basis as the ASI output. The first mode in
which the data is sparsely output is called Byte mode, and the second mode in
which the data is output on a packet-by-packet basis is called Packet mode.
In Byte mode, the data sent from A12 board is output as they are. In Packet
mode, data processing is required. The data is organized into a packet within the
Link chip and then output. The Packet controller is not used in this process. The
Packet controller must be set to Byte mode.
In through mode where the data is sent from the ASI input to the ASI output, the
data does not pass through the packet controller circuit and are output with the
same timing as the ASI input.
Packet Mode Operation.
The FIFO shift register is used to output the data on a
packet-by-packet basis. This FIFO has 9 bits of width, and its depth is 512
stages. The content of 9-bit width is 8 bit for data, and 1 bit for Sync Bit. The
Sync Bit indicates the location of sync pattern (47h) in the data.
The data sent from the A12 board is fed to the FIFO. The FIFO output port
searches for a Sync Bit. When a Sync Bit is detected, data output from the FIFO
is stopped, and the data that follows the Sync Bit is stored to the FIFO.
The FIFO input port also searches for a Sync Bit. When the port detects a Sync
Bit in the next packet, it sends the detection to the read-out controller at the
FIFO output port. When the FIFO output port receives the Sync Bit detection
signal from the input port, the output port reads out the signals until the next
packet Sync Bit is detected. The data rate of FIFO input port is equal to the data
transfer rate of MTX100A, and that of the output port is 216 Mbps (with a clock
of 27 MHz), which is used for the ASI output.
The partial transport stream is a bit stream generated by removing the transport
packets unrelated to selected audio/video program(s) from MPEG-2 transport
packets. In transmitting/receiving multiple numbers of audio/video programs
with a lower data rate through a high-speed data line, the packets in a single
audio/video program are transmitted as intermittent packets compressed along
the time axis. In this case, the period of time between the packets has some
meaning. When recording data in the MTX100A, all the packets are recorded as
a serial data. When reproducing such data, the time information between packets
are lost and the data becomes a serial data.
To resolve the problem mentioned above, the period of time between the
received packets are measured, and the timing information is added before the
Sync byte of each packet as 4 bytes data. In reproducing the data, the timing
information located before the next packet is derived after the packet is output.
Partial TS Controller
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