Theory of Operation
2-8
MTX100A MPEG Recorder & Player Service Manual
The next packet is output after waiting for the period of time as written in this
four bytes of data.
Partial TS Controller 1.
The Partial TS Controller 1 picks up 4 bytes of data
located before sync byte from the data stream sent from A12 board, and counts
down the value written in this 4 bytes data with the 27 MHz clock. When the
count becomes zero, the controller starts the processing on the next packet.
While waiting for the next sync byte, the controller outputs The Busy signal to
stop the operation of A12 board. The packet size that can be handled by the
Partial TS Controller 1 is fixed to 192 bytes/packet (188 + 4). When sending
packets of other sizes, turn the Partial TS processing off. This board uses only 24
bits out of 32 bits (4 bytes) of Time Stamp information. The upper 8 bits are
ignored.
Partial TS Controller 2.
This controller performs the opposite operation to that of
the Partial TS Controller 1. It counts the period of time between the packets
being received with the 27 MHz clock, and adds the result of counting to the top
of the next packet as the time information of 4 bytes. Because a 24-bit counter is
used, the first byte of 4 bytes of data becomes zero. While 4 bytes of information
is output, the controller stops input of packets. The controller has the FIFO shift
register of 9 bit x 256 to retain the data during the suspension period.
Although the packets received from IEEE1394 or from ASI contain Sync Pattern
(47h), the 47h may be contained within data or the 47h may be missing because
of an error. The sync detector reconfigures information indicating the sync
location and delivers the information to the next block together with the data. In
the output circuit of IEEE1394, the packets are generated based upon this sync
location information. In the Partial TS Controller, the measurements of time
interval between packets are performed based upon this information.
Sync Detector 1.
The Sync Detector 1 produces sync location information to be
delivered to IEEE1394 output circuit. This information is also used to send the
received packet size to the application. This circuit is compatible with the packet
sizes of 188, 204, and 208. After repeated confirmation that “47h” is located at
the same location (188, 204, or 208) for five (5) times, the circuit starts to output
the sync location information. When the circuit failed to find the location of
“47h” for three consecutive times, it stops outputting the sync location informa-
tion. The circuit sends information of 1, 2, or 3 to the application when the
packet size is 188, 204, or 208, respectively. Otherwise, it sends information of
zero (0). This information is needed to use the through mode for the IEEE1394
output.
Sync Detector
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