Tektronix AWG70001A, Техническое описание

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Speci fi cations
Table 1-21: Trigger input (cont.)
Characteristics Description
Minimum pulse width
1 k Ω selected 20 ns
50 Ω selected 20 ns
Trigger delay to analog output Asynchronous trigger mode: 32,480 / (2 * fclk) ±20 ns
Synchronous trigger mode: 30,880 / (2 * fclk) ±20 ns
fclk is the frequency of the DAC sampling clock
The DAC sampling clock frequency is displayed on the clock settings tab when the external
clock output is enabled.
Trigger hold off 8320/fclk ±20 ns
fclk is the frequency of the DAC sampling clock
Trigger hold off is the amount of delay required at the end of a waveform before another trigger
pulse can be processed.
Trigger asynchronous jitter The asynchronous jitter performance is directly proportional the frequency of the DAC sampling
clock. The DAC sampling clock frequency is displayed on the clock settings tab when the
external clock output is enabled.
1 k Ω selected 130 ps
p-p
, 26 ps
rms
for 6.25 GHz DAC sampling clock
90 ps
p-p
, 17 ps
rms
for 12.5 GHz DAC sampling clock
50 Ω selected 105 ps
p-p
, 24 ps
rms
s for 6.25 GHz DAC sampling clock
70 ps
p-p
, 14 ps
rms
for 12.5 GHz DAC sampling clock
Trigger synchronous jitter Clock In = 12.5 GHz: 300 fs
rms
, 4.2 ps RJ
p-p
BER@10-12
Variable Reference In = 156.25 MHz: 400 fs
rms
s, 5.6 ps RJ
p-p
BER@10-12
Fixed Reference In = 10 MHz: 1.7 ps rms, 23.8 ps RJ
p-p
BER@10-12
Sample rate = 25 GS/s Trigger input impedance = 50 Ω
Table 1-22: Reference clock input
Characteristics Description
Connector type SMA on rear panel
Input impedance 50 Ω (AC coupled)
Input amplitude –5 dBm to +5 dBm
Frequency range 10 MHz ±100 ppm
Variable frequency range 35 MHz to 240 MHz.
Acceptable frequency drift while the instrument is operating is ± 0.1%.
Table 1-23: Sync clock output
Characteristics Description
Connector type SMA on rear panel
Output impedance 50 Ω (AC coupled)
AWG70000A Series and AWGSYNC01 Technical Reference 1–15