Tektronix 1730 Series, Инструкция по эксплуатации

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1730–Series Theory of Operation
4–12
COMPARATOR
VCO
LINE
RATE
SYNC
H SYNC
Figure 4-4: Simplified representation of the AFC phase-lock loop.
The Comp Sync, from the Sync Separator on Diagram 1, drives the timing input
to U735. U735 is a registered 16-input gate array that outputs line rate enables
and SYNC. The line rate SYNC output drives U844B, a non-retriggerable
one-shot that outputs a pulse wide enough to lock out the twice line rate pulses
in the vertical interval. The line rate signal, output from pin 5 (Q), drives the
Back Porch Generator (U844A), the Horizontal AFC phase-lock loop (U644),
and the sweep trigger selector (U535).
U644 is a phase-locked loop. See Figure 4-4. In this application a second
comparator, U947B, is used to drive the internal VCO. The circuit’s input,
through pin 14, is line rate sync. R536 and C545 form an adjustable delay
network that ensures filter or input switching occurs during H Sync time.
U644 has a VCO as one of the onboard functions. Its timing components (C643,
R742, and R743) keep the oscillator frequency near line sync rate. When there is
line rate sync the output of the comparator will be approximately equal to the
U947B + input dc level and no correction voltage will be input to the VCO.
If line rate sync is interrupted, the VCO runs at, or near, line rate until sync is
restored. When line rate sync is restored it will be out of phase with the VCO
and the internal comparator (U644) will have an output indicating that the loop is
unlocked. With an unbalanced input, the second comparator outputs an error
signal that will: 1. Attempt to charge the loop filter. 2. Drive the VCO voltage
input. When the VCO output changes to a new frequency, the comparator output
changes; however, the charge on the loop filter reduces the effect of this change
on the comparator in order to slow the loop response. When the loop nears lock
the amount of change is very small.
Having H Sync generated by this AFC circuit allows the 1730-Series to sync up
on noisy syncs and remain synced up on signals with missing H rate sync pulses.
U841D is used as an inverter to output the required HSYNC.
Horizontal Sync Generator