Tektronix 1730 Series, Инструкция по эксплуатации

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1730–Series Theory of Operation
4–6
The external sync signal from the rear-panel EXT REF loop-through is buffered
by an operational amplifier consisting of U795A and B. It has a gain of –1,
which is determined by the combination of input resistor (R
i
) R997 and feedback
resistor (R
f
) R898. The operational amplifier output drives Q798, which is one
current source for the Source Switch (U795D).
The internal sync current source, for the other side of the common emitter Source
Switch (U795D), is Q792. It provides signal current through pin 5 of U795D
which also forward biases CR696 when the switching signal (EXT) is high.
CR698 keeps CR696 from conducting when external sync input is selected.
When external sync is selected, EXT (from the Microprocessor Diagram 5) goes
low, turning on U795 (pins 1, 2, & 3) so that signal current from Q798 (the
external sync current source) forward biases CR697. The 0.5 mA of signal
current from Q798 (external) or Q792 (internal) drives into a common base
stage, Q799, which develops a 1 V video signal across R797.
The Sync Stripper removes the active video portions of the signal to generate the
sync required for timing signals. The circuit detects the sync tip, stretches it
(amplifies that portion of the signal), and generates a clean sync signal. The
circuit responds well to pulses up to 1 MHz, then rolls off to eliminate any effect
from subcarrier or high frequency noise at the sync level.
The Sync Stripper circuit consist of a two-stage amplifier and a clamp (or dc
restorer). Figure 4-2 shows a simplified schematic of the circuit. Both amplifier
stages feed back sync level information to the clamp.
The first stage of the amplifier inverts the video signal and clips it near the sync
tip. (The bandwidth of the Sync Stripper keeps the circuit from clamping to high
frequency components of the video signal.) This operational amplifier stage is
made up of Q992 and U892C. The gain setting resistors R993 (R
i
) and R992
(R
f
) let the amplifier provide high gain to the sync tip portion of the signal, but
clip any signal components slightly above the sync level.
During sync time, the clamp circuit maintains the output of the first amplifier
stage at about +5 V, which is fed back to the clamp circuit, through CR990, to
maintain the proper level.
During non-sync times (active video), CR988 and CR989 are both on to shunt
U892C and greatly reduce the gain. Shunting the active video limits the
saturation of U892C, which allows it to respond quickly to the next sync
transition.
External Sync Input and
Source Switch
Sync Stripper