MAINBOARD BIOS SETUP
MAINBOARD BIOS SETUP
P6L40-A4E
P6L40-A4E User’s Manual
User’s Manual
29
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installed. Here, greater delays may be required to preserve the integrity of the data held in
the slower memory chips.
DRAM Speed Selection
- DRAM timing is controlled by the DRAM timing registers. The
timings programmed into this register are dependent on the system design. 60ns is the
fastest rate. The 70ns timing is slower and may be required in certain system designs to
support loose layouts or slower memory.
MA Wait State
- This item determines the
wait state before the assertion of the first MA
and CAS#/RAS# assertion during DRAM read or write leadoff cycle. Options are
slow
and
fast
(default).
EDO RAS# To CAS# Delay
- This option allows you to determine the number of clocks
allocated between the assertion of RAS# To CAS#. Options are
3
or
2
Clocks. *Default =
2
Clocks
. This has no impact on page hit cases and affects only row and page misses.
EDO RAS# Precharge Time
- DRAM must continually be refreshed or it will lose its data.
Normally, DRAM is refreshed entirely as the result of a single request. This option allows
you to determine the number of CPU clocks allocated for the
R
ow
A
ddress
S
trobe to
accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh
may be incomplete and data will be lost. Options are
3
or
4
Clocks. *Default =
4 Clocks
.
EDO DRAM Read Burst
- Sets the burst mode read timing for EDO DRAM. Burst read
and write requests are generated by the CPU in four separate parts. The first part provides
the location within the DRAM where the read or write is to take place, while the remaining
three parts provide the actual data. The lower the timing numbers, the faster the system will
address memory. Options are
x333
(default) and
x222
.
EDO DRAM Write Burst
- Sets the timing for burst mode writes from DRAM. Burst read
and write requests are generated by the CPU in four separate parts. The first part provides
the location within the DRAM where the read or write is to take place, while the remaining
three parts provide the actual data. The lower the timing numbers, the faster the system will
address memory. Options are
x333
and
x222
(default).
DRAM Data Integrity Mode
- When set at
Non-ECC
(default), there will be no memory
errors shown on the monitor for
Memory parity SERR# (NMI)
. When parity DRAM
modules are used, select
ECC
(Error Checking and Correcting) to correct 1 bit memory
errors in the memory.
CPU-To-PCI IDE Posting
- When disabled, the CPU to PCI IDE posting cycles will be
treated as normal I/O write transactions.
System BIOS Cacheable
- When
Enabled
, the contents of the F0000h system memory
segment can be cached to the Level-2 cache memory. The contents of the F0000h memory
segment are always copied from the BIOS ROM to system RAM for faster execution and
PCI compliance.
