MAINBOARD BIOS SETUP
MAINBOARD BIOS SETUP
P6F40-B5 User’s Manual
P6F40-B5 User’s Manual
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DRAM Leadoff Timing
- Controls the DRAM leadoff timing. Slower leadoffs may be
required in certain system designs to support slower memories.
Disabled
is the default.
Read-Around-Write
- When
Enabled
(Default), the execution efficiency of the processor
will be increased. When there is no dependence between the read and write commands, this
would allow the processor to execute read commands out of order.
PCI Burst Write Combine
- When
Enabled
(Default), the execution efficiency of the PCI
bus will be increased by combining several CPU to PCI write cycles into one. VGA
performance will also be increased via this setting.
PCI-To-DRAM Pipeline
- When
Enabled
(Default), the bandwidth of the path between the
PCI and DRAM will be increased to enhance the PCI bus efficiency and DRAM accessing.
CPU-To-PCI Write Post
- When
Enabled
(Default), the efficiency of PCI bus is increased
and processor execution is accelerated.
USWC Write Posting
- When
Enabled
(Default), allows USWC (Uncacheable,
Speculatable, Write-Combining) write posting during I/O bridge access.
CPU-To-PCI IDE Posting
- When
Enabled
(Default), the CPU to PCI IDE posting cycles
will be treated as normal I/O write transactions.
System BIOS Cacheable
- When
Enabled
(Default), the contents of the F0000h system
memory segment can be read from or written to the Level-2 cache memory. The contents of
the F0000h memory segment are always copied from the BIOS ROM to system RAM for
faster execution.
Video RAM Cacheable
-
Enabled
will cause access to the video BIOS addressed at
C0000H to C7FFFH to be cached and also let the B0000H to BFFFFH to be a USWC
memory type. *
Disabled
is the default.
8 Bit I/O Recovery Time
- The recovery time is the length of time, measured in ISA BUS
clocks, that the system will delay after the completion of an input/output request. This delay
takes place because the CPU is operating faster than the input/output bus. Therefore the
CPU must be delayed to allow for the completion of I/O transfers. This item allows you to
determine the recovery time allowed for 8 bit I/O. Choices are from NA, 1 to 8 ISA BUS
clocks. *
NA
is the default.
16 Bit I/O Recovery Time
- This item allows you to determine the recovery time allowed
for 16 bit I/O. Choices are from NA, 1 to 4 ISA BUS clocks. *
NA
is the default.
Memory Hole At 15M-16M
- In order to improve performance, certain space in memory
can be reserved for ISA cards. This memory must be mapped into the memory space below
16 MB. *
Disabled
is the default.
