Tekram Technology P6F40-B5, Руководство пользователя

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MAINBOARD BIOS SETUP MAINBOARD BIOS SETUP
P6F40-B5 User’s Manual P6F40-B5 User’s Manual
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C8000-DFFFF Shadow - These options control the location of the contents of the 16KB
expansion card ROMs beginning at the specified memory location. If no adapter ROM is
using the named ROM area, this area is made available to the local bus. Shadowing a ROM
reduces the memory available between 640KB and 1024KB by the amount used for this
purpose. The settings are
Enabled or Disabled .
CHIPSET FEATURES SETUP
This setup menu contains advanced configuration options relating to the mainboard chipset.
These options are rarely changed by the user.
Auto Configuration : Enabled 8 Bit I/O Recovery Time : 1
DRAM Speed Selection : 70ns 16 Bit I/O Recovery Time : 1
DRAM RAS# Precharge Time : 4 T Memory Hole At 15M-16M : Disabled
MA Additional Wait State : Disabled Passive Release : Enabled
RAS# To CAS# Delay : Enabled Delayed Transaction : Disabled
DRAM Read Burst (B/E/F) : x2/3/4
DRAM Write Burst (B/E/F) : x3/3/3
ISA Bus Clock : PCI CLK/4
DRAM Refresh Type : CBR
DRAM ECC/PARITY Select : Disabled
DRAM Leadoff Timing : Disabled
Read-Around-Write : Enabled
PCI Burst Write Combine : Enabled
PCI-To-DRAM Pipeline : Enabled
CPU-To-PCI Write Post : Enabled
ESC : Quit
↑ ↓ → ←
: Select
USWC Write Posting : Enabled F1 : Help PU/PD/+/- : Mod
CPU-To-PCI IDE Posting : Enabled F5 : Old Values (Shift) F2 : Color
System BIOS Cacheable : Disabled F6 : Load BIOS Defaults
Video RAM Cacheable : Disabled F7 : Load Setup Defaults
Auto Configuration - When Enabled , pre-defined values for DRAM, Cache, Timings, etc.
are set according to the CPU type & system clock. Enabled is the recommended setting.
These settings are only editable when Auto Configuration is Disabled .
Note: The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if data
is being lost. Such a scenario might occur if your system had mixed speed DRAM chips
installed. Here, greater delays may be required to preserve the integrity of the data held in
the slower memory chips.
DRAM Speed Selection - DRAM timing is controlled by the DRAM timing registers. The
timings programmed into this register are dependent on the system design. 60ns is the
fastest rate. The 70ns timing is slower and may be required in certain system designs to
support loose layouts or slower memory.