MAINBOARD BIOS SETUP
MAINBOARD BIOS SETUP
P6F40-B5 User’s Manual
P6F40-B5 User’s Manual
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DRAM RAS# Precharge Time
- DRAM must continually be refreshed or it will lose its
data. Normally, DRAM is refreshed entirely as the result of a single request. This option
allows you to determine the number of CPU clocks allocated for the
R
ow
A
ddress
S
trobe to
accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh
may be incomplete and data will be lost. Options are
3
or
4
Clocks. *Default =
4 CPU
Clocks
.
MA Additional Wait State
-
Enabled
would insert one additional wait state before the
assertion of the first MA and CAS#/RAS# assertion during DRAM read or write leadoff
cycle. And no clock would be inserted for
Disabled
(Default).
RAS# To CAS# Delay
-
Enabled
(Default) would insert one clock between assertion of
RAS# and CAS#. And no clock would be inserted for
Disabled
. This has no impact on page
hit cases and affects only row and page misses.
DRAM Read Burst (B/E/F)
- Sets the burst mode read timing for three different DRAM
types - (
B
EDO/
E
DO/
F
PM). Burst read and write requests are generated by the CPU in four
separate parts. The first part provides the location within the DRAM where the read or
write is to take place, while the remaining three parts provide the actual data. The lower the
timing numbers, the faster the system will address memory. *
x2/3/4 timing
is the default.
x2/3/4
Read DRAM (BEDO/EDO/FPM) timings are 2-2-2/3-3-3/4-4-4
x2/2/3
Read DRAM (BEDO/EDO/FPM) timings are 2-2-2/2-2-2/3-3-3
x3/4/4
Read DRAM (BEDO/EDO/FPM) timings are 3-3-3/4-4-4/4-4-4
DRAM Write Burst (B/E/F)
- Sets the timing for burst mode writes from DRAM. Burst
read and write requests are generated by the CPU in four separate parts. The first part
provides the location within the DRAM where the read or write is to take place, while the
remaining three parts provide the actual data. The lower the timing numbers, the faster the
system will address memory. *
x3/3/3 timings
is the default.
x2/2/3
Write DRAM timings (BEDO/EDO/FPM) are 2-2-2/2-2-2/3-3-3
x3/3/3
Write DRAM timings (BEDO/EDO/FPM) are 3-3-3/3-3-3/3-3-3
x3/3/4
Write DRAM timings (BEDO/EDO/FPM) are 3-3-3/3-3-3/4-4-4
x4/4/4
Write DRAM timings (BEDO/EDO/FPM) are 4-4-4/4-4-4/4-4-4
ISA Bus Clock
- This item allows you to select the PCI clock type. PCI CLK/3 or PCI
CLK/4 (Default).
DRAM Refresh Type
- Two options: CBR (CAS# Before RAS#; Default) and RAS only.
DRAM ECC/PARITY Select
- When
Disabled
(Default), there will be no memory errors
shown on the monitor for
Memory parity SERR# (NMI)
. When parity DRAM modules are
used, you may select
Parity
or
ECC
(Error Checking and Correcting) to correct 1 bit
memory errors in the memory.
