TS-7300 MANUAL
CONNECTORS AND HEADERS
The following steps outline the software execution to use the Cirrus A/D converter:
1. Unlock the software lock before setting the TSEN bit in the ADCClk register by writing
0xAA to the ADCSWLock register (0x8090_00C0). “OR” in the TSEN bit (bit 31) to the
ADCClkDiv register (0x8093_0090)
2. Unlock the software lock (again) before OR'ing in the ADCEN (ADC clock enable, bit
31) to 0x8093_0080
3. Clear bit 2, the ADCPD (ADC Power Down) bit, at 0x8093_0080. This bit MUST be set
to 0 (see page 91 of the EP9301 User's Guide)
4. After unlocking the software lock, write the channel's magic value (see Cirrus EP9301
User's Guide, table 20-2) to the ADCSwitch register (0x8090_0018) to select that
channel for the next data acquisition
5. Poll the ADCResult register (0x8090_0008) until bit 31 is not set
6. Using a 32 bit read operation, read the result from 0x8090_0008, masking off the upper
16 bits
Interpreting Cirrus A/D Converter
The Cirrus on-chip A/D converter is a successive approximation A/D converter. Each A/D
channel is calibrated on the
TS-7300
and these 16-bit values are stored in non-volatile
EEPROM. These calibration values minimize the offset errors and gain errors in the
EP9302 A/D. It is important for the user program to use these values as per our sample
code, which can be found either on our website or in the CD included in the Developer's
Kit. Two reference points, 0 and 2.5 Volts, with the corresponding reference values stored
in EEPROM. Bytes 0x07EB through 0x07FE of the EEPROM hold a two dimensional
array:
[channel number][0V ref. point, 2.5V ref. Point]
The reference points are stored as a 16 bit value, and should be used to correlate the
values returned by the Cirrus A/D converter to voltage.
5.11 DIO2 Header
The
TS-7300
provides up to 35 DIO lines connected straight to the FPGA through the
FPGA DIO header. The FPGA DIO is a 40-pin header divided in 2 sub-headers of 20 pins
each. The first header is unamed on the board, while the second is called DIO2. The 40
total FPGA DIO lines can also be used as a FPGA connected expansion bus instead of
the CPU connected regular PC104 expansion bus.
The default TS-BITSTREAM provided with
TS-7300
enables hardware functionality for
VGA video. This default bitstream maps the VGA video signals to the first 20-pin FPGA
DIO header (unamed one). The 17 total video signals can be changed to XDIO lines if the
video is disabled on the FPGA bitstream. The following is the numbering scheme for this
header:
Table: FPGA DIO Pin-out (first header)
GND
RED0 RED1 RED2 RED3 RED4 HSYN VSYN OEV
+5V
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
BLU0 BLU1 BLU2 BLU3 BLU4 GRN0 GRN1 GRN2 GRN3 GRN4
Pin #20 of this header is fused +5V (polyfuse), and pin #2 is ground. Pin #18 can be
externally driven high to disable DB15 VGA connector DACs.
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