TS-7300 MANUAL
CONNECTORS AND HEADERS
Table: DIO1 Header Pin Configuration
DIO1 Pin
Default Signal
TS-7300
1
DIO_0
2
GND
3
DIO_1
4
Port_C0
EXT_RESET
5
DIO_2
DIO_8
6
SPI_Frame
7
DIO_3
8
DIO_8
ADC4
9
DIO_4
10
SPI_MISO
11
DIO_5
12
SPI_MOSI
13
DIO_6
14
SPI_CLK
15
DIO_7
16
+3.3 V
DIO_8 is accessed via bit 1 of Port F in the EP9302. The Port F data register is at address
location
0x8084_0030
. The DDR address for this port is location
0x8084_0034
.
The Pin 4 of the DIO1 Header, in the default configuration, is accessed via bit 0 of Port C
in the EP9302. The address location
0x8084_0008
is Port C Data Register and
0x8084_0018
is Port C Directon Register.
When accessing these registers, it is important not to change the other bit positions in
these Port F registers. Other DIO1 Port functionality, used for dedicated
TS-7300
functions, utilize these same control registers. All accesses to these registers should use
read-modify-write cycles.
!
Warning
All pins on the DIO header use 0-3.3V logic levels. Do not drive these lines to 5V.
When the DIO pins are configured as outputs, they can “source” 4 mA or “sink” 8 mA and
have logic swings between GND and 3.3V. When configured as inputs, they have
standard TTL level thresholds and must not be driven below 0 Volts or above 3.3 Volts.
DIO lines DIO_0 thru DIO_3 have 4.7K Ohm “pull-up” resistors to 3.3V biasing these
signals to a logic”1”. The other DIO pins have 100K Ohm bias resistors biasing these
inputs to a logic “1”.
Note
On the TS-7300 some of the pins on the DIO1 header (Pin 1/DIO_0, Pin 3/DIO_1,
Pin 7/DIO_3, Pin 9/DIO_4) are used for DMA operations during bootup by the SD
card driver and therefore they will be driven as outputs. In order to use these pins
as GPIO pins DMA will need to be disabled programming the following registers:
*(sysc 0xC0) = 0xAA; //SFTWR_LCK register
*(sysc 0x80) = 0x08140d00; //DEVICE_CFG register
Refer to the
EP9301 User's Guide
for further information on SYSCON registers.
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