TS-7300 MANUAL
COMMON INTERFACES GENERAL INFORMATION
4 COMMON INTERFACES GENERAL INFORMATION
The purpose of this section is to provide general information about the common
interfaces, such as Serial Ports and Digital Input/Output, which appear in more than one
header or connector of the
TS-7300
. For further information on these features, refer to the
Connectors and Headers section of this manual.
4.1 Serial Ports
The
TS-7300
have two asynchronous serial ports (COM1 and COM2) which provide a
means to communicate with external serial devices. Each is independently configured as
a 16C550- type COM port that is functionally similar to a standard PC COM port. These
ports have 16-byte FIFOs in both the receive and the transmit UART channels. Both COM
ports can support all standard baud rates up through 230.4Kbaud. Both COM ports may
be configured to use a DMA channel (useful when very high baud rates are being used).
COM1 and COM2 UARTs can generate:
✔
Four individually maskable interrupts from the receive, transmit, and modem status
logic blocks
✔
A single, combined interrupt that is asserted if any of the individual interrupts are
asserted and unmasked
The COM1 port can also support the HDLC protocol. Refer to the Cirrus EP9301 User's
Guide for more details. The COM2 port can optionally support RS-485 half or full duplex
levels.
The
TS-7300
has either six or ten total asynchronous serial ports and the capability to add
more on-board via the PC/104 Expansion Bus.
Two serial ports are standard on-board and are available through the COM1 (DB9 and 10-
pin header) and COM2 (10-pin header) interfaces. They use RS232 signal level and 16
bytes FIFO. The minimum and maximum baud rate are 110bps and 230.4Kbps,
respectively. In addition, COM2 is RS-485 capable.
Four RS-232 COM ports are integrated on the FPGA and are available through the
COM3, COM4, COM5 and COM6 10-pin headers by default. Extra four COM ports from
the FPGA may be provided using the same headers. Each is independently configured
and is functionally similar to a PC COM port. ALL FPGA COM ports can operate in 8-bit
mode or 9-bit mode. The minimum and maximum baud rate are 2400bps and 115.2Kbps,
respectively.
4.2 Digital I/O
There are 55 total Digital Input/Output (DIO) lines available on the
TS-7300
. These are
available on three headers labeled “DIO”, “LCD” and “DIO2”. The header labeled LCD can
be used as 11 DIO lines or as an alphanumeric LCD interface. The header labeled DIO
has 8 DIO pins available. In addition to the DIO signals, each header also has a power pin
and Ground available. The LCD header has 5V power available while the DIO header has
3.3V power.
The DIO2 header (FPGA DIO) is controlled by the on-board FPGA. It is a 40-pin header
divided in two sub-headers of 20 pins each. On the first header, by default, there are 17
video signals that can be changed into digital I/O, while the second, labeled DIO2, has 18
digital I/O lines which implement two XDIO ports. Thus, there are 35 total DIO lines
connected directly to the on-board FPGA on the
TS-7300
available through the 40-pin
header. The first header has 5V power available and the second (DIO2) has 3.3V power.
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